Appearance inspection apparatus and method in which plural threads are processed in parallel

a technology of appearance inspection and processing method, which is applied in the direction of program control, instruments, semiconductor/solid-state device testing/measurement, etc., can solve the problems of imposing a limitation on high-speed processing, limitation of image data, and second prior art problem similar to the first prior art, etc., and achieves simple configuration and high speed

Inactive Publication Date: 2006-01-17
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0014]Therefore, an object of the present invention is to provide an appearance inspection apparatus and an appearance inspection method that can execute an appearance inspection at a high speed, irrespectively of a simple configuration.

Problems solved by technology

Thus, an overhead for the assignment is large to thereby impose a limitation on a high-speed processing.
Thus, this second prior art also has the problem similar to that of the first prior art.
Thus, the overhead is large to thereby result in the limitation on the high-speed processing of the image data.
Hence, the configuration of the image processor is complex, and the size thereof is large.

Method used

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  • Appearance inspection apparatus and method in which plural threads are processed in parallel
  • Appearance inspection apparatus and method in which plural threads are processed in parallel
  • Appearance inspection apparatus and method in which plural threads are processed in parallel

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first embodiment

(First Embodiment)

[0050]In the appearance inspection apparatus according to the first embodiment of the present invention, one inspection region on image data is divided into four sub-regions. The image data on the respective sub-regions are processed in parallel by using four CPUs. The case of the void inspection will be described below as an example. It should be noted that, in this first embodiment, “n” of the present invention is “4”, “k” of the present invention is “3” and “m” of the present invention is “1”.

[0051]In this void inspection, “Binary Conversion Process”, “Inversion Process”, “Area Measurement Process”, and “Inspection Judgement Process” are sequentially carried out. In the “Binary Conversion Process”, an image data, which is sent from the camera 19 through the data input controller 18 and the system bus 20 and stored in the memory 14, is converted into a binary value. In the “Inversion Process”, the binary value is inverted to thereby generate binary image data. In...

second embodiment

(Second Embodiment)

[0073]An appearance inspection apparatus according to a second embodiment of the present invention will be described below. The appearance inspection apparatus according to the first embodiment is designed such that all the processes, such as the binary conversion process, the inversion process and the area measurement process, are executed in parallel to each other by the plurality of threads. However, the appearance inspection apparatus according to the second embodiment is designed such that a particular process in the above-mentioned plurality of processes is executed by a single thread. It should be noted that, in this second embodiment, “n” of the present invention is “4”, “k” of the present invention is “2” and “m” of the present invention is “1”.

[0074]A thread generation process to be executed at the time of a void inspection firstly calculates a size of a void inspection region. Then, it is checked whether or not this calculated size is greater than a pre...

third embodiment

(Third Embodiment)

[0086]An appearance inspection apparatus according to a third embodiment of the present invention is designed as follows. That is, when executing a process that is difficult to carry out a parallel process, for example, such as a histogram process or a projection process, if there are a plurality of inspection regions, each sub-region is processed by one thread.

[0087]FIG. 6 shows an example of image data of an IC to be used in this third embodiment. In the void inspection, the void inspection region is set on the package portion of the IC, as described in the first and second embodiments.

[0088]In an inter-lead extraneous material inspection, first to fourth inter-lead extraneous material inspection regions are set for each side, in a lead portion of the IC. Then, four threads are generated correspondingly to the first to fourth inter-lead extraneous material inspection regions. In each of threads, a procedure for carrying out the inter-lead extraneous material insp...

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Abstract

An appearance inspection apparatus is composed of a memory 14, a thread generator and a plurality of CPUs 10 to 13. The memory 14 stores image data of an appearance of an IC. The thread generator generates a thread in which a procedure is described for independently processing the image data stored in the memory 14 and storing the processing result into the memory 14. The plurality of CPUs 10 to 13 for executing the plurality of threads generated by the thread generator, in parallel. Thus, this can provide an appearance inspection apparatus and an appearance inspection method that can execute an appearance inspection at a high speed, irrespectively of a simple configuration.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to an appearance inspection apparatus and an appearance inspection method for carrying out an appearance inspection by processing a large amount of image data. More particularly, the present invention relates to a technique for processing the image data in parallel.[0003]2. Description of the Related Art[0004]Conventionally, an appearance inspection apparatus has been known for inspecting an appearance of an integrated circuit (IC) by processing image data generated by photographing the IC. As such an appearance inspection apparatus, for example, Japanese Laid Open Patent Application (JP-A-Heisei, 11-259434) discloses “Parallel Data Processor And Appearance Inspection Apparatus Including It” (hereafter, referred to as a first prior art). In this appearance inspection apparatus, a data input portion driven by a synchronous pulse from a drive signal bus receives image data and then transfers ...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06K9/54G06K9/60G01N21/88G01N21/956G01R31/311G01R31/319G06F15/16G06T1/00G06T1/20H01L21/66
CPCG01R31/311G01R31/319H01L22/12G06T1/00
Inventor SASAKI, YOSHIHIRONAGAO, MASAHIKO
Owner RENESAS ELECTRONICS CORP
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