49 results about "Fault attack" patented technology

The invention discloses a security protection method based on an SM9 signature algorithm, operation time is determined according to the value of a random number, the operation time is random, in addition, point multiplication operation time is also random, and timing attacks can be resisted; according to the method, secret key masking operation is carried out on a private key of a user, meanwhile, randomization operation is carried out on operands of point multiplication in point multiplication operation, the private key is not leaked in the process of adopting an NAF point multiplication operation algorithm and a signature algorithm, and meanwhile, full-process masking is carried out in the middle process, so that power consumption, electromagnetism and secret key information have no correlation; energy power consumption and electromagnetic attack can be resisted; whether related parameter variables are tampered or whether errors are injected or not can be detected by comparing hash operation before algorithm starting and point multiplication operation; in addition, after signature is completed, verification operation is carried out on the signature value once, whether all parameter variables and intermediate variables are tampered or whether errors are injected in the whole-process operation can be detected, and fault attacks can be resisted.

The invention discloses a security protection method based on an SM9 decryption algorithm, which masks a private key by using a random number, randomizes the operand of point multiplication, does not leak the private key in the whole decryption algorithm process, and performs full-flow masking in the middle process, so that power consumption, electromagnetism and key information are free from correlation, and the security of the decryption algorithm is improved. Therefore, energy power consumption and electromagnetic attack can be resisted; the operation time is determined according to the value of the random number, and when the NAF point multiplication operation is adopted, the point multiplication operation time of the random window is random, so that the timing attack can be resisted; when the KDF function is used for operation, a ct randomization mode is adopted, and sensitive information is prevented from being leaked; by comparing SM3 hash operation values before and after the SM3 hash operation values, whether the parameter variables are tampered or whether errors are injected is effectively detected; and encryption operation is carried out on the decrypted plaintext, so that whether all parameter variables and intermediate variables are tampered or whether errors are injected in the whole-process operation can be detected, and therefore, fault attacks can be resisted.

The invention belongs to the technical field of information security, and discloses a method for evaluating the anti-differential fault analysis capability of 5-bit S box candidates in an NIST LWC competition, which comprises the following steps of: 1, injecting a fault into the input of a 5-bit S box applied to a target lightweight encryption algorithm, deducing the input of the 5-bit S box through an output authentication tag obtained through analysis, and determining the input of the 5-bit S box according to the input of the 5-bit S box; the middle state in the password operation process is reconstructed before the 5-bit S box layer, and the key is indirectly obtained through the middle state; 2, evaluating the anti-differential fault analysis capability of the target lightweight encryption algorithm according to the differential fault attack result in the step 1; and step 3, designing the target lightweight encryption algorithm according to the anti-differential fault analysis capability evaluation result of the target lightweight encryption algorithm. According to the invention, the security of the LWC algorithm in the face of differential fault attack is improved.

Efficient side-channel and fault attack countermeasures for cryptographic execution circuitry are described. In certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: execution circuitry to generate a cryptographic signature for a first input of a message value and a second input of a secret key value, and countermeasure circuitry to, in response to a request to generate the cryptographic signature, cause the execution circuitry to perform multiple sequential executions for the first input of the message value, the second input of the secret key value, and a third input of a different uniformly random value for each execution to generate a plurality of cryptographic signatures, and output, as a resultant for the request, one of the plurality of cryptographic signatures as the cryptographic signature.

The present invention relates to a method for securing against fault attacks the execution of the verification of a Crystals-Dilithium post-quantum digital signature σ of a message M comprising a challenge seed c̃, a test vector z and a hint vector of polynomials h generated with a secret key sk = (ρ, K, tr, s1, s2, t0), said digital signature verification taking as inputs, said digital signature σ, said message M and a public key pk = (ρ, t1) and comprising a step of ensuring that a fault attack aiming at verifying one of the conditions P1, P2 and P3 does not lead to accept a forged signature, where : ct1.2d=0, ‖ct1.2d‖∞<βand‖LowBitsq(Az−ct1.2d,2γ2‖∞<γ2−β, ‖ct1.2d‖∞<γ2.

The application relates to the fields of network communication anomaly detection and intelligent operation and maintenance, in particular to a behavior reasoning and AI intelligent disposal method and system for communication anomalies, which comprises the following steps: collecting communication interaction time sequence data and protocol stack resource state data; constructing an ideal communication state model based on interface contract analysis results, protocol specification analysis results and queuing rules, and generating an ideal communication track benchmark according to a service request sequence in a preset time window; respectively performing fault attack knowledge injection and service load fluctuation rule injection to generate abnormal scene simulation tracks and service tide simulation tracks; performing difference calculation on real observation features and the ideal communication track benchmark to obtain a real residual space, and generating an abnormal theoretical residual space and a service tide theoretical residual space; generating abnormal type results and root cause results based on the topological similarity between the residual spaces, and outputting corresponding intelligent disposal instructions; and the application can accurately identify high-concurrency legal tides and real attacks.

Systems and techniques are provided for secure processing. For instance, a process can include: providing an input value to generate a first output value; obtaining a plurality of first intermediate output values based on a function of the first output value and a tweak value; embedding the plurality of first intermediate output values into a mathematical structure; obtaining a plurality of second intermediate output values, wherein the plurality of second intermediate output values are a function of the plurality of first intermediate output values, a random number, and an inverse of the tweak value; determining a most common value of the plurality of second intermediate output values; obtaining a third intermediate value, the third intermediate value based on a function of the most common value and an inverse of the random number; projecting the third intermediate value from the mathematical structure to obtain a second output value for output.

A semiconductor device is protected from glitch attacks (FIA). A reset data transfer controller RDTC executes N times of data transfer, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer, and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparison circuit CMP1 determines the match / mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs, and outputs a determination result signal RS representing the determination result. A system controller SYSC activates a processor PRC when the determination result signal RS indicates a match, and causes the reset data transfer controller RDTC to execute the N times of data transfer again when it indicates a mismatch.

Method for improving the resilience of an electronic device to fault attacks, corresponding computer program product and devices A method is proposed for improving the resilience of an electronic device to fault attacks, the electronic device implementing a fault detection mechanism during the execution of a command. According to such method, the electronic device executes: - executing a command; and - executing, after a predetermined period of time counted from the end of the execution of the command, at least one operation changing the internal state of the electronic device to an internal state indicative that a fault was detected or not during the execution of the command.

This invention discloses a stream cipher implementation method based on FSR and fourth-order CA, including designing the stream cipher algorithm structure, component design of LFSR and NFSR, setting CA rules for register updates, designing a keystream generation function, algorithm initialization, keystream generation, and algorithm encryption / decryption. CA rules are used to update registers, and each internal state bit is a bitwise feedback bit at each stage of algorithm execution. In the initial loading stage, the LFSR and NFSR are loaded using an initial key and initial vector, and the remaining bits of the LFSR are padded with the initial key. The keystream initialization stage uses 32 iterations, ensuring the key and vector are fully obfuscated within the register's internal state. This invention uses fourth-order CA rules combined with register design to provide good differential properties and nonlinearity for the cryptographic algorithm. The key expansion used to padded the LFSR during the initialization stage effectively resists differential analysis and fault attacks.

To protect a semiconductor device from a glitch attach (FIA).SOLUTION: A reset data transfer controller RDTC executes N times data transfer, transfers data DT stored in a first memory MEM1a to a main register REGm during first data transfer, and transfers the data DT stored in the first memory MEM 1a to a sub register REGs during the Nth data transfer. A comparison circuit CMP1 determines matching / mismatching between the data DTm transferred to the main register REGm and the data DTs transferred to the sub register REGs, and outputs a determination result signal RS representing a determination result. A system controller SYSC starts a processor PRC if the determination result signal RS represents the matching, and re-executes data transfer N times to the reset data transfer controller RDTC if it represents the mismatching.SELECTED DRAWING: Figure 3B

A semiconductor device is protected against glitch attacks (FIA). A reset data transfer controller (RDTC) performs N data transfers, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparator circuit (CMP1) determines the match / mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs and outputs a determination result signal RS representing the determination result. A system controller (SYSC) activates a processor (PRC) when the determination result signal RS indicates a match and causes the reset data transfer controller (RDTC) to re-execute the N data transfers when it indicates a mismatch.

The present invention provides a two-party collaborative EdDSA signature algorithm resistant to differential fault attacks, including: step one, P1 and P2 jointly generate the required secret key; wherein P1 is the first participant and P2 is the second participant; step two, P1 and P2 interact to generate a signature (R, s); step three, the signature (R, s) is verified. The present invention designs a two-party collaborative EdDSA digital signature algorithm resistant to differential fault attacks, which not only has the advantages of high security, easy verification, smaller secret key and signature space, but also the entire signature process must be jointly participated in by both communicating parties to generate a two-party collaborative signature, reducing the risk of signature private key leakage, resisting excessive concentration of signer rights, preventing single point failure, and enhancing the security of the signature algorithm; in addition, by introducing random numbers into the signature algorithm, malicious attacks are prevented from injecting faults into the EdDSA signature process using physical means such as electromagnetic radiation and lasers, and the key information of the cryptographic system is analyzed and inferred, thereby protecting the asset security of the currency.

A data processing component includes a fault attack shielding and detection arrangement. Specifically, the data processing component includes a first layer and a second layer. The first layer includes a first data processing element, the first data processing element configured to receive a control input and to execute a predetermined operation on the control input to generate a control output; and a first comparator configured to compare the control output with an expected control output, and to generate a fault status signal if the control output is different from the expected control output. The second layer includes a second data processing element identical to the first data processing element, configured to receive a first operational input and to execute the same predetermined operation on the first operational input to generate a first operational output. The data processing component may include a computer processor.

A method is provided for detecting a fault attack when performing a process including a plurality of operations. The method comprises identifying a group of operations selected from the plurality of

A method is provided for detecting a fault attack when performing a process including a plurality of operations. The method comprises identifying a group of operations selected from the plurality of operations and performing operations from the group of operations in a random order such that each operation is repeated n times where n is less than or equal to a security parameter corresponding to a maximum number of potential fault attacks. The results of the n repetitions of each operation are compared to determine whether the output value of each repetition of the operation is the same. In a case that the output value of each repetition is not the same an action to record or mitigate a fault attack is performed.

The present invention discloses a security protection method based on the SM9 decryption algorithm. The method masks a private key with a random number and performs a random operation on the operands of the point multiplication. The private key is not leaked during the entire decryption algorithm process. At the same time, the intermediate processes are fully masked, so that power consumption, electromagnetic and key information are unrelated, thereby being able to resist energy consumption and electromagnetic attacks. Since the operation time is determined according to the value of the random number, when the NAF point multiplication operation is adopted, the point multiplication operation time of the random window is also random, thereby being able to resist timing attacks. When the KDF function is used for operation, a CT randomization method is adopted to avoid leaking sensitive information. By comparing the previous and next SM3 hash operation values, it is effectively detected whether the parameter variables have been tampered with or whether there is error injection. The decrypted plaintext is encrypted again, and it is possible to detect whether all parameter variables and intermediate variables in the full-process operation have been tampered with or whether there is error injection, thereby being able to resist fault attacks.

The present application relates to a kind of fault attack methods for RIPEMD-160 hash algorithm, first randomly generates to be handled message, and to be handled message is as the input of RIPEMD-160 algorithm, using random single byte fault model, in the fifth round of import random 8 bits fault, obtains error output.Based on error output, deduce intermediate state value, then using statistical method, calculate the hamming weight of intermediate state value, according to the minimum value of hamming weight, the correct value of corresponding message is obtained.Repeat the process of importing fault and analysis, finally the complete message to be handled can be deduced.The method provided by the present application is easy to implement, fast and high accuracy, and provides important analysis basis for the security research of RIPEMD-160 hash algorithm.

The detection unit (101) detects vulnerabilities to fault attacks contained in the program code (210). The correction unit (103) corrects the program code (210) to address the vulnerabilities detected by the detection unit (101). The determination unit (102) determines whether or not the corrected program code (130) corrected by the correction unit (103) has vulnerabilities to fault attacks.

The application relates to a method for detecting that an Ascon algorithm resists impossible statistical fault analysis, first, a plaintext to be processed is randomly generated, an Ascon authentication encryption algorithm is used to process the plaintext message, in this stage, the processing process is interfered with to induce faults, error output is obtained to obtain an error label; then, through a decryption algorithm and a statistical method, an intermediate state value is calculated, the probability of occurrence of each value is counted, key candidate values leading to intermediate state values which are theoretically impossible to obtain are excluded, key candidate values making the probability of occurrence of the intermediate state values most conform to ideal conditions are selected, the fault introduction and analysis process are repeated for multiple times, and then, a complete key is recovered. The application is easy to implement, fast and high in accuracy, and provides a good analysis basis for the security research of the Ascon authentication encryption algorithm resisting impossible statistical fault attacks.

A detection unit (101) detects vulnerability to fault attacks contained in program code (210). A correction unit (103) makes a correction to the program code (210) to address the vulnerability detected by the detection unit (101). A determination unit (102) determines whether or not vulnerability to fault attacks is present in corrected program code (130) after the correction has been made by the correction unit (103).

This invention discloses a lightweight authentication encryption algorithm differential fault attack method, relating to the fields of cryptography and information security technology; it initializes the AEGIS encryption algorithm and injects a random single-bit fault, with plaintext P as input. i The method involves encrypting the AEGIS encryption algorithm after initialization to generate correct and incorrect ciphertexts and obtaining their output difference. The output difference between the correct and incorrect ciphertexts is then XORed, and the location of the fault is determined using the XOR result. Byte state recovery is then performed based on the XOR result, and the word state recovery process is repeated. Finally, the inverse round function formula and encryption formula are applied to restore the complete internal state. This invention employs a lightweight authentication encryption algorithm differential fault attack method, which can efficiently extract key features from complex high-dimensional time-series data and accurately identify potential fault modes.

The present invention relates to the technical field of device testing, and particularly to a method and system for testing the ability of fault attacks based on Hamming weight, including fault response classification, establishment of a fault leakage function, selection of an effective time attack window, and selection of voltage glitches for fault injection attacks; selection of an effective fault injection parameter interval, and injecting a large number of faults within the above time window; according to the response distribution of each slice within the time window, selecting any appropriate combination of fault parameters, and reducing the entropy of the unknown key of the target device by analyzing the fault information. The present invention grasps the essence of the fault based on the fault probability of Hamming weight, accurately establishes a leakage model, has low requirements for data, strong fault tolerance, greatly reduces the data volume compared with the existing model, has good practicability, and solves the problem that most of the existing leakage models have certain limitations and cannot simultaneously take into account the requirements for data, data volume, fault tolerance, and attack efficiency.

This application discloses an encryption method and apparatus. The method includes: obtaining data to be encrypted and a first key; wherein the first key is obtained through a primitive key arrangement algorithm; if the final key of the first key is obtained through a differential fault attack, and the initial key of the first key is obtained through the final key and a constructed impossible differential path, then the primitive key arrangement algorithm is updated; based on the initial key and the updated primitive key arrangement algorithm, a second key is determined; and the data to be encrypted is encrypted using the second key.

The present invention discloses a security protection method based on the SM9 signature algorithm. The method determines the operation time according to the value of a random number. The operation time is random. In addition, the point multiplication operation time is also random, which can resist timing attacks. A key mask operation is performed on the user's private key. At the same time, the point multiplication operands are randomized in the point multiplication operation. The NAF point multiplication algorithm is used. The private key is not leaked during the signature algorithm. At the same time, the intermediate process is fully masked, so that power consumption, electromagnetic and key information are unrelated, and the method can resist energy consumption and electromagnetic attacks. By comparing the hash operation at the beginning of the algorithm and before the point multiplication operation, it can detect whether the relevant parameter variables have been tampered with or whether there is error injection. In addition, after the signature is completed, a verification operation is performed on the signature value. It can detect whether all parameter variables and intermediate variables in the full process operation have been tampered with or whether there is error injection, which can resist fault attacks.

This application provides a method for detecting latent fault attacks in the SILC authentication encryption algorithm, comprising: acquiring multiple authentication tags output by the target encryption device to obtain a tag set; setting multiple sets of subkey candidate sets; wherein each set of subkey candidate sets corresponds to a fault import position, and the subkey candidate set exhaustively lists all subkey candidate values ​​affected by the fault after the fault is imported at the corresponding fault import position; determining whether the master key can be recovered based on the tag set and each set of subkey candidate sets; if so, determining that the target encryption device has suffered a latent fault attack within a preset period. This scheme helps to detect and respond to latent fault attacks that may lead to master key leakage or encryption system failure as early as possible, effectively ensuring the encryption security of the target encryption device and the confidentiality and integrity of related information.

The invention relates to a semiconductor device. A semiconductor device is protected from fault attack (FIA). A reset data transfer controller (RDTC) performs N data transfers, transfers data (DT) stored in a first memory (MEM1a) to a main register (REGm) during a first data transfer, and transfers data (DT) stored in the first memory (MEM1a) to a sub-register (REG) during an Nth data transfer. A comparison circuit CMP1 determines a match / mismatch between data DTm transferred to a main register REGm and data DT transferred to a sub-register REG, and outputs a determination result signal RS indicating a determination result. When it is determined that the result signal RS indicates a match, the system controller SYSC activates the processor PRC, and when it indicates a mismatch, the reset data transfer controller RDTC is caused to perform N data transfers again.

The application discloses a combined threshold mask protection method of Ascon authentication encryption algorithm, which combines threshold implementation with exchange-based infection technology, and comprises the following steps: constructing a second-order threshold implementation of the Ascon algorithm; copying a complete copy of the constructed second-order threshold mask as a redundant mask; and reducing the number of additional random numbers used by the exchange technology based on the copy through the exchange bit sharing selection algorithm provided by the application, and exchanging part of the sharing selected. The method has the advantages that the Ascon algorithm can effectively resist second-order power consumption attacks and first-order differential fault attacks, only a small amount of additional random numbers and a small circuit implementation area are needed, and the hardware implementation cost can be significantly reduced.

The invention relates to methods, and associated devices, for protecting the execution of the generation of a Crystals-Dilithium digital signature σ of a message M with a secret key sk against attacks exploiting invalid signatures content by fault attacks. In order to prevent an attacker bypassing by fault injection attacks tests on a second test vector (I) from obtaining invalid signatures as outputs of the signature generation algorithm, the invention modifies the norm check performed on the second test vector (I) in such a way that if this check is skipped, the candidate signature is rejected by the subsequent test performed on a fourth vector of polynomials h.