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13 results about "Fault attack" patented technology

What is Fault Attack. 1. A fault attack is an intentional manipulation of the integrated circuit or its state, with the aim to provoke an error within the integrated circuit in order to move the device into an unintended state. The goal is to access security critical information or to disable internal protection mechanisms.

A behavior reasoning and AI intelligent handling method and system for communication anomalies

ActiveCN122247760BAttackAnomaly detection
The application relates to the fields of network communication anomaly detection and intelligent operation and maintenance, in particular to a behavior reasoning and AI intelligent disposal method and system for communication anomalies, which comprises the following steps: collecting communication interaction time sequence data and protocol stack resource state data; constructing an ideal communication state model based on interface contract analysis results, protocol specification analysis results and queuing rules, and generating an ideal communication track benchmark according to a service request sequence in a preset time window; respectively performing fault attack knowledge injection and service load fluctuation rule injection to generate abnormal scene simulation tracks and service tide simulation tracks; performing difference calculation on real observation features and the ideal communication track benchmark to obtain a real residual space, and generating an abnormal theoretical residual space and a service tide theoretical residual space; generating abnormal type results and root cause results based on the topological similarity between the residual spaces, and outputting corresponding intelligent disposal instructions; and the application can accurately identify high-concurrency legal tides and real attacks.
Owner:ZHEJIANG SCI-TECH UNIV

Data processing component and computer processor

PendingUS20260187291A1Computer hardwareEngineering
A data processing component includes a fault attack shielding and detection arrangement. Specifically, the data processing component includes a first layer and a second layer. The first layer includes a first data processing element, the first data processing element configured to receive a control input and to execute a predetermined operation on the control input to generate a control output; and a first comparator configured to compare the control output with an expected control output, and to generate a fault status signal if the control output is different from the expected control output. The second layer includes a second data processing element identical to the first data processing element, configured to receive a first operational input and to execute the same predetermined operation on the first operational input to generate a first operational output. The data processing component may include a computer processor.
Owner:NAGRAVISION SRL

Detection of fault attacks

A method is provided for detecting a fault attack when performing a process including a plurality of operations. The method comprises identifying a group of operations selected from the plurality of
Owner:PQSHIELD LTD

Detection of fault attacks

A method is provided for detecting a fault attack when performing a process including a plurality of operations. The method comprises identifying a group of operations selected from the plurality of operations and performing operations from the group of operations in a random order such that each operation is repeated n times where n is less than or equal to a security parameter corresponding to a maximum number of potential fault attacks. The results of the n repetitions of each operation are compared to determine whether the output value of each repetition of the operation is the same. In a case that the output value of each repetition is not the same an action to record or mitigate a fault attack is performed.
Owner:PQSHIELD LTD

A Differential Fault Attack Method for Lightweight Authentication Encryption Algorithms

This invention discloses a lightweight authentication encryption algorithm differential fault attack method, relating to the fields of cryptography and information security technology; it initializes the AEGIS encryption algorithm and injects a random single-bit fault, with plaintext P as input. i The method involves encrypting the AEGIS encryption algorithm after initialization to generate correct and incorrect ciphertexts and obtaining their output difference. The output difference between the correct and incorrect ciphertexts is then XORed, and the location of the fault is determined using the XOR result. Byte state recovery is then performed based on the XOR result, and the word state recovery process is repeated. Finally, the inverse round function formula and encryption formula are applied to restore the complete internal state. This invention employs a lightweight authentication encryption algorithm differential fault attack method, which can efficiently extract key features from complex high-dimensional time-series data and accurately identify potential fault modes.
Owner:HENAN UNIV OF SCI & TECH

Encryption methods and devices

This application discloses an encryption method and apparatus. The method includes: obtaining data to be encrypted and a first key; wherein the first key is obtained through a primitive key arrangement algorithm; if the final key of the first key is obtained through a differential fault attack, and the initial key of the first key is obtained through the final key and a constructed impossible differential path, then the primitive key arrangement algorithm is updated; based on the initial key and the updated primitive key arrangement algorithm, a second key is determined; and the data to be encrypted is encrypted using the second key.
Owner:LENOVO (BEIJING) LTD

Method for protecting performance of verification of post-CRYSTALS-DIITHIUM quantum signatures from fault attacks

The invention relates to a method for protecting the performance of a verification of a post-Crystal-Diithium quantum digital signature [sigma] of a message M, comprising a challenge seed, a test vector z and a polynomial hint vector h, generated using a secret key sk = ([rho], K, tr, s1, s2, t0), said digital signature verification verifying said digital signature [sigma], said message M and a public key pk = ([rho], K, tr, s1, s2, t0), said digital signature verification verifying said digital signature [sigma], said message M and said public key pk = ([rho], K, tr, s1, s2, t0). The invention relates to a method for verifying one of conditions P1, P2 and P3 (t1, t1) as input and comprising the following steps: ensuring that a fault attack intended to verify one of the conditions P1, P2 and P3 does not result in a signature accepting forgery, where: P1: ct1.2 d = 0, and.
Owner:THALES DIS FRANCE SA

Chip real-time detection method and device, chip and storage medium

The application discloses a kind of real-time detection method, device and chip of chip, storage medium, the method includes: when receiving any detection circuit sends alarm signal, first check algorithm and second check algorithm are used respectively to check signal and obtain first check signal and second check signal, the detection circuit is correspondingly set with each module of the chip;When the first check signal and the second check signal fail to compare, the chip is triggered to reset operation or self-destruction operation;By using first check algorithm and second check algorithm to check signal and carry out check operation, and the state of different check signals is compared, when state is inconsistent, it is determined that alarm signal is attacked, and alarm signal is fed back to application, with the effect of resisting multi-point fault attack.
Owner:BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD +2

Differential fault attack method for lightweight cipher gift based on byte model

The application discloses a differential fault attack method of a lightweight cipher GIFT based on a byte model, and comprises the following steps: obtaining correct cipher texts generated by using the GIFT algorithm to encrypt plaintexts without injecting byte faults and error cipher texts generated by encrypting the plaintexts after injecting byte faults, wherein the GIFT algorithm is encrypted through a plurality of S boxes; performing an exclusive or operation on the correct cipher texts and the error cipher texts to obtain output differentials of each corresponding S box in the encryption process of target plaintexts, and determining a target S box injected with a byte fault in the plurality of S boxes according to the output differentials of each S box and input differentials of each S box obtained in advance; determining an input value of the target S box in the encryption process of plaintexts without injecting byte faults as a correct input value of the target S box according to the input differentials and the output differentials of the target S box; and recovering an encryption key used by the plaintexts without injecting byte faults and the plaintexts with injecting byte faults through the correct input value of the target S box.
Owner:HENAN UNIV OF SCI & TECH

A cascading failure vulnerability testing system, method, and related devices

The application discloses a kind of cascading failure vulnerability test system, method set related device, including: routing exchange module, fault / attack event simulation module, vulnerability test module, wherein the routing exchange module is used to set the bandwidth reduction of current routing exchange system's routing link and reconstruct to routing node function;The fault / attack event simulation module is used to simulate the current routing exchange system based on preset fault / attack event after reconstruction is completed;The vulnerability test module is used to test and evaluate the cascading failure vulnerability of the current routing exchange system after simulation is completed.The above-mentioned system, routing exchange, fault / attack simulation and vulnerability test are carried out based on virtualization environment, and large-scale network can be constructed based on virtual environment, and large-scale routing node can be reproduced.
Owner:BEIJING DINGNIU TECH CO LTD +1

Distributed system password service platform and method supporting secure access and resource management and control

The invention discloses a distributed system password service platform and method supporting security access and resource management and control, and belongs to the technical field of data security. Step 2) terminal attribute authentication and password request; 3) password fragment generation and edge distribution; and 4) performing security access and on-chain auditing. A dynamic strategy engine based on attribute-based encryption is designed, attributes such as user identity, role and environment label are bound with resource authority in real time, fine-grained access control and resource dynamic management and control are realized, authority strategy change is ensured to take effect immediately, secret keys do not need to be distributed in advance or tokens do not need to be updated, and user experience is improved. The traditional token hijacking risk is thoroughly eliminated; and second-level permission revocation is realized. On the basis of a distributed password fragmentation storage and threshold key management architecture, the high concurrency performance is improved, it is ensured that single-point fragmentation leakage cannot be decrypted, single-point fault attack is resisted, and dual optimization of safety and efficiency is achieved.
Owner:THREE GORGES INTELLIGENT ENG CO LTD

Data processing assembly and computer processor

A data processing component includes a fault attack shielding and detection arrangement. Specifically, the data processing component comprises: a first layer comprising: a first data processing element configured to receive a control input and perform a predetermined operation on the control input to generate a control output; and a first comparator configured to compare the control output with an expected control output and generate a fault condition signal if the control output is different from the expected control output; and a second layer including a second data processing element identical to the first data processing element, configured to receive the first operation input and perform an identical predetermined operation on the first operation input to generate a first operation output. A computer processor may include the data processing component.
Owner:NAGRAVISION SA