58 results about "Fault attack" patented technology

The invention discloses a security protection method based on an SM9 signature algorithm, operation time is determined according to the value of a random number, the operation time is random, in addition, point multiplication operation time is also random, and timing attacks can be resisted; according to the method, secret key masking operation is carried out on a private key of a user, meanwhile, randomization operation is carried out on operands of point multiplication in point multiplication operation, the private key is not leaked in the process of adopting an NAF point multiplication operation algorithm and a signature algorithm, and meanwhile, full-process masking is carried out in the middle process, so that power consumption, electromagnetism and secret key information have no correlation; energy power consumption and electromagnetic attack can be resisted; whether related parameter variables are tampered or whether errors are injected or not can be detected by comparing hash operation before algorithm starting and point multiplication operation; in addition, after signature is completed, verification operation is carried out on the signature value once, whether all parameter variables and intermediate variables are tampered or whether errors are injected in the whole-process operation can be detected, and fault attacks can be resisted.

The invention discloses a security protection method based on an SM9 decryption algorithm, which masks a private key by using a random number, randomizes the operand of point multiplication, does not leak the private key in the whole decryption algorithm process, and performs full-flow masking in the middle process, so that power consumption, electromagnetism and key information are free from correlation, and the security of the decryption algorithm is improved. Therefore, energy power consumption and electromagnetic attack can be resisted; the operation time is determined according to the value of the random number, and when the NAF point multiplication operation is adopted, the point multiplication operation time of the random window is random, so that the timing attack can be resisted; when the KDF function is used for operation, a ct randomization mode is adopted, and sensitive information is prevented from being leaked; by comparing SM3 hash operation values before and after the SM3 hash operation values, whether the parameter variables are tampered or whether errors are injected is effectively detected; and encryption operation is carried out on the decrypted plaintext, so that whether all parameter variables and intermediate variables are tampered or whether errors are injected in the whole-process operation can be detected, and therefore, fault attacks can be resisted.

The invention belongs to the technical field of information security, and discloses a method for evaluating the anti-differential fault analysis capability of 5-bit S box candidates in an NIST LWC competition, which comprises the following steps of: 1, injecting a fault into the input of a 5-bit S box applied to a target lightweight encryption algorithm, deducing the input of the 5-bit S box through an output authentication tag obtained through analysis, and determining the input of the 5-bit S box according to the input of the 5-bit S box; the middle state in the password operation process is reconstructed before the 5-bit S box layer, and the key is indirectly obtained through the middle state; 2, evaluating the anti-differential fault analysis capability of the target lightweight encryption algorithm according to the differential fault attack result in the step 1; and step 3, designing the target lightweight encryption algorithm according to the anti-differential fault analysis capability evaluation result of the target lightweight encryption algorithm. According to the invention, the security of the LWC algorithm in the face of differential fault attack is improved.

Efficient side-channel and fault attack countermeasures for cryptographic execution circuitry are described. In certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: execution circuitry to generate a cryptographic signature for a first input of a message value and a second input of a secret key value, and countermeasure circuitry to, in response to a request to generate the cryptographic signature, cause the execution circuitry to perform multiple sequential executions for the first input of the message value, the second input of the secret key value, and a third input of a different uniformly random value for each execution to generate a plurality of cryptographic signatures, and output, as a resultant for the request, one of the plurality of cryptographic signatures as the cryptographic signature.

Systems and techniques are provided for secure processing. For instance, a process can include: providing an input value to generate a first output value; obtaining a plurality of first intermediate output values based on a function of the first output value and a tweak value; embedding the plurality of first intermediate output values into a mathematical structure; obtaining a plurality of second intermediate output values, wherein the plurality of second intermediate output values are a function of the plurality of first intermediate output values, a random number, and an inverse of the tweak value; determining a most common value of the plurality of second intermediate output values; obtaining a third intermediate value, the third intermediate value based on a function of the most common value and an inverse of the random number; projecting the third intermediate value from the mathematical structure to obtain a second output value for output.

The present invention relates to a method for securing against fault attacks the execution of the verification of a Crystals-Dilithium post-quantum digital signature σ of a message M comprising a challenge seed c̃, a test vector z and a hint vector of polynomials h generated with a secret key sk = (ρ, K, tr, s1, s2, t0), said digital signature verification taking as inputs, said digital signature σ, said message M and a public key pk = (ρ, t1) and comprising a step of ensuring that a fault attack aiming at verifying one of the conditions P1, P2 and P3 does not lead to accept a forged signature, where : ct1.2d=0, ‖ct1.2d‖∞<βand‖LowBitsq(Az−ct1.2d,2γ2‖∞<γ2−β, ‖ct1.2d‖∞<γ2.

A method, system and apparatus for fault attack simulation. A circuit design and a fault attack simulation model are obtained that defines characteristics of a multi-click attack to be simulated in a circuit. The fault attack simulation model defines at least a number of hits during a multi-strike attack, a time window simulating the multi-strike attack, and a list of potentially attacked circuit elements of the circuit during the multi-strike attack. Based on the fault attack simulation model, a plurality of fault attacks are generated that follow the fault attack simulation. Each generated fault attack includes a plurality of hits occurring for the list of potentially attacked circuit elements during a time window. The resulting fault attack is simulated using a hardware simulator that simulates the circuit design. And outputting the simulation result to the user.

The invention relates to the technical field of fault attacks, and discloses a fault injection method, system and device for an FPGA chip and a medium. The method comprises the following steps: acquiring actual power consumption data of an FPGA chip on a time sequence in a process of running a preset encryption algorithm by the FPGA chip; simulating the process of running the preset encryption algorithm by the FPGA chip to obtain simulation power consumption data of the FPGA chip on a time sequence; respectively carrying out multiplication operation and accumulation operation on data at corresponding moments in the actual power consumption data and the simulation power consumption data, and acquiring moments corresponding to the actual power consumption data and the simulation power consumption data when values obtained by the multiplication operation and the accumulation operation exceed a preset threshold value as fault injection moments of the FPGA chip; at the fault injection moment, the voltage drop is generated in the FPGA chip to complete fault injection of the FPGA chip, and the fault injection can be realized without changing the original circuit of the FPGA or triggering a signal.

The application relates to the fields of network communication anomaly detection and intelligent operation and maintenance, in particular to a behavior reasoning and AI intelligent disposal method and system for communication anomalies, which comprises the following steps: collecting communication interaction time sequence data and protocol stack resource state data; constructing an ideal communication state model based on interface contract analysis results, protocol specification analysis results and queuing rules, and generating an ideal communication track benchmark according to a service request sequence in a preset time window; respectively performing fault attack knowledge injection and service load fluctuation rule injection to generate abnormal scene simulation tracks and service tide simulation tracks; performing difference calculation on real observation features and the ideal communication track benchmark to obtain a real residual space, and generating an abnormal theoretical residual space and a service tide theoretical residual space; generating abnormal type results and root cause results based on the topological similarity between the residual spaces, and outputting corresponding intelligent disposal instructions; and the application can accurately identify high-concurrency legal tides and real attacks.

A data processing component comprises a fault attack shielding and detection arrangement. Specifically, the data processing component comprises: a first layer comprising: a first data processing element, the first data processing element configured to receive a control input and to execute a predetermined operation on the control input to generate a control output; and a first comparator configured to compare the control output with an expected control output, and to generate a fault status signal if the control output is different from the expected control output; and a second layer comprising: a second data processing element identical to the first data processing element, configured to receive a first operational input and to execute the same predetermined operation on the first operational input to generate a first operational output. A computer processor may comprises the data processing component.

Systems and techniques are provided for secure processing. For instance, a process can include: providing an input value to generate a first output value; obtaining a plurality of first intermediate output values based on a function of the first output value and a tweak value; embedding the plurality of first intermediate output values into a mathematical structure; obtaining a plurality of second intermediate output values, wherein the plurality of second intermediate output values are a function of the plurality of first intermediate output values, a random number, and an inverse of the tweak value; determining a most common value of the plurality of second intermediate output values; obtaining a third intermediate value, the third intermediate value based on a function of the most common value and an inverse of the random number; projecting the third intermediate value from the mathematical structure to obtain a second output value for output.

A semiconductor device is protected from glitch attacks (FIA). A reset data transfer controller RDTC executes N times of data transfer, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer, and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparison circuit CMP1 determines the match / mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs, and outputs a determination result signal RS representing the determination result. A system controller SYSC activates a processor PRC when the determination result signal RS indicates a match, and causes the reset data transfer controller RDTC to execute the N times of data transfer again when it indicates a mismatch.

Method for improving the resilience of an electronic device to fault attacks, corresponding computer program product and devices A method is proposed for improving the resilience of an electronic device to fault attacks, the electronic device implementing a fault detection mechanism during the execution of a command. According to such method, the electronic device executes: - executing a command; and - executing, after a predetermined period of time counted from the end of the execution of the command, at least one operation changing the internal state of the electronic device to an internal state indicative that a fault was detected or not during the execution of the command.

This invention discloses a stream cipher implementation method based on FSR and fourth-order CA, including designing the stream cipher algorithm structure, component design of LFSR and NFSR, setting CA rules for register updates, designing a keystream generation function, algorithm initialization, keystream generation, and algorithm encryption / decryption. CA rules are used to update registers, and each internal state bit is a bitwise feedback bit at each stage of algorithm execution. In the initial loading stage, the LFSR and NFSR are loaded using an initial key and initial vector, and the remaining bits of the LFSR are padded with the initial key. The keystream initialization stage uses 32 iterations, ensuring the key and vector are fully obfuscated within the register's internal state. This invention uses fourth-order CA rules combined with register design to provide good differential properties and nonlinearity for the cryptographic algorithm. The key expansion used to padded the LFSR during the initialization stage effectively resists differential analysis and fault attacks.

To protect a semiconductor device from a glitch attach (FIA).SOLUTION: A reset data transfer controller RDTC executes N times data transfer, transfers data DT stored in a first memory MEM1a to a main register REGm during first data transfer, and transfers the data DT stored in the first memory MEM 1a to a sub register REGs during the Nth data transfer. A comparison circuit CMP1 determines matching / mismatching between the data DTm transferred to the main register REGm and the data DTs transferred to the sub register REGs, and outputs a determination result signal RS representing a determination result. A system controller SYSC starts a processor PRC if the determination result signal RS represents the matching, and re-executes data transfer N times to the reset data transfer controller RDTC if it represents the mismatching.SELECTED DRAWING: Figure 3B

A semiconductor device is protected against glitch attacks (FIA). A reset data transfer controller (RDTC) performs N data transfers, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparator circuit (CMP1) determines the match / mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs and outputs a determination result signal RS representing the determination result. A system controller (SYSC) activates a processor (PRC) when the determination result signal RS indicates a match and causes the reset data transfer controller (RDTC) to re-execute the N data transfers when it indicates a mismatch.

The present invention provides a two-party collaborative EdDSA signature algorithm resistant to differential fault attacks, including: step one, P1 and P2 jointly generate the required secret key; wherein P1 is the first participant and P2 is the second participant; step two, P1 and P2 interact to generate a signature (R, s); step three, the signature (R, s) is verified. The present invention designs a two-party collaborative EdDSA digital signature algorithm resistant to differential fault attacks, which not only has the advantages of high security, easy verification, smaller secret key and signature space, but also the entire signature process must be jointly participated in by both communicating parties to generate a two-party collaborative signature, reducing the risk of signature private key leakage, resisting excessive concentration of signer rights, preventing single point failure, and enhancing the security of the signature algorithm; in addition, by introducing random numbers into the signature algorithm, malicious attacks are prevented from injecting faults into the EdDSA signature process using physical means such as electromagnetic radiation and lasers, and the key information of the cryptographic system is analyzed and inferred, thereby protecting the asset security of the currency.

Systems and techniques are provided for secure processing. For instance, a process can include: providing an input value to generate a first output value; obtaining a plurality of first intermediate output values based on a function of the first output value and a tweak value; embedding the plurality of first intermediate output values into a mathematical structure; obtaining a plurality of second intermediate output values, wherein the plurality of second intermediate output values are a function of the plurality of first intermediate output values, a random number, and an inverse of the tweak value; determining a most common value of the plurality of second intermediate output values; obtaining a third intermediate value, the third intermediate value based on a function of the most common value and an inverse of the random number; projecting the third intermediate value from the mathematical structure to obtain a second output value for output.

A data processing component includes a fault attack shielding and detection arrangement. Specifically, the data processing component includes a first layer and a second layer. The first layer includes a first data processing element, the first data processing element configured to receive a control input and to execute a predetermined operation on the control input to generate a control output; and a first comparator configured to compare the control output with an expected control output, and to generate a fault status signal if the control output is different from the expected control output. The second layer includes a second data processing element identical to the first data processing element, configured to receive a first operational input and to execute the same predetermined operation on the first operational input to generate a first operational output. The data processing component may include a computer processor.

The invention provides a hidden fault attack detection method for an SILC authentication encryption algorithm, and the method comprises the steps: obtaining a plurality of authentication tags outputted by target encryption equipment, and obtaining a tag set; setting a plurality of groups of sub-key candidate sets; wherein each group of sub-key candidate sets corresponds to one fault import position, and the sub-key candidate sets exhausts all sub-key candidate values affected by the fault after the fault is imported at the corresponding fault import position; judging whether the master key can be recovered according to the label set and each group of sub-key candidate sets; and if yes, judging that the target encryption equipment is subjected to the hidden fault attack in the preset period. According to the scheme, hidden fault attacks possibly causing leakage of the master key or failure of the encryption system can be found and handled as early as possible, and the encryption security of the target encryption equipment and the confidentiality and integrity of related information are powerfully guaranteed.

A method is provided for detecting a fault attack when performing a process including a plurality of operations. The method comprises identifying a group of operations selected from the plurality of

The invention relates to a method for detecting impossible statistical fault analysis resistance of an Ascon algorithm, which comprises the following steps of: firstly, randomly generating a plaintext to be processed, processing a plaintext message by using an Ascon authentication encryption algorithm, interfering a processing process in the stage, inducing the plaintext message to generate a fault, and obtaining error output to obtain an error label; calculating an intermediate state value through a decryption algorithm and a statistical method, counting the occurrence probability of each value, eliminating key candidate values which cause the occurrence of the intermediate state value which is theoretically impossible to obtain, and selecting key candidate values which enable the occurrence probability of the intermediate state value to most conform to an ideal condition; and the fault introduction and analysis process is repeated for multiple times, so that a complete key is recovered. The method is easy to implement, high in speed and high in accuracy, and a good analysis basis is provided for security research of an Ascon authentication encryption algorithm for resisting impossible statistical fault attacks.

A method is provided for detecting a fault attack when performing a process including a plurality of operations. The method comprises identifying a group of operations selected from the plurality of operations and performing operations from the group of operations in a random order such that each operation is repeated n times where n is less than or equal to a security parameter corresponding to a maximum number of potential fault attacks. The results of the n repetitions of each operation are compared to determine whether the output value of each repetition of the operation is the same. In a case that the output value of each repetition is not the same an action to record or mitigate a fault attack is performed.

The present invention discloses a security protection method based on the SM9 decryption algorithm. The method masks a private key with a random number and performs a random operation on the operands of the point multiplication. The private key is not leaked during the entire decryption algorithm process. At the same time, the intermediate processes are fully masked, so that power consumption, electromagnetic and key information are unrelated, thereby being able to resist energy consumption and electromagnetic attacks. Since the operation time is determined according to the value of the random number, when the NAF point multiplication operation is adopted, the point multiplication operation time of the random window is also random, thereby being able to resist timing attacks. When the KDF function is used for operation, a CT randomization method is adopted to avoid leaking sensitive information. By comparing the previous and next SM3 hash operation values, it is effectively detected whether the parameter variables have been tampered with or whether there is error injection. The decrypted plaintext is encrypted again, and it is possible to detect whether all parameter variables and intermediate variables in the full-process operation have been tampered with or whether there is error injection, thereby being able to resist fault attacks.

The present application relates to a kind of fault attack methods for RIPEMD-160 hash algorithm, first randomly generates to be handled message, and to be handled message is as the input of RIPEMD-160 algorithm, using random single byte fault model, in the fifth round of import random 8 bits fault, obtains error output.Based on error output, deduce intermediate state value, then using statistical method, calculate the hamming weight of intermediate state value, according to the minimum value of hamming weight, the correct value of corresponding message is obtained.Repeat the process of importing fault and analysis, finally the complete message to be handled can be deduced.The method provided by the present application is easy to implement, fast and high accuracy, and provides important analysis basis for the security research of RIPEMD-160 hash algorithm.

The detection unit (101) detects vulnerabilities to fault attacks contained in the program code (210). The correction unit (103) corrects the program code (210) to address the vulnerabilities detected by the detection unit (101). The determination unit (102) determines whether or not the corrected program code (130) corrected by the correction unit (103) has vulnerabilities to fault attacks.

The application relates to a method for detecting that an Ascon algorithm resists impossible statistical fault analysis, first, a plaintext to be processed is randomly generated, an Ascon authentication encryption algorithm is used to process the plaintext message, in this stage, the processing process is interfered with to induce faults, error output is obtained to obtain an error label; then, through a decryption algorithm and a statistical method, an intermediate state value is calculated, the probability of occurrence of each value is counted, key candidate values leading to intermediate state values which are theoretically impossible to obtain are excluded, key candidate values making the probability of occurrence of the intermediate state values most conform to ideal conditions are selected, the fault introduction and analysis process are repeated for multiple times, and then, a complete key is recovered. The application is easy to implement, fast and high in accuracy, and provides a good analysis basis for the security research of the Ascon authentication encryption algorithm resisting impossible statistical fault attacks.

A detection unit (101) detects vulnerability to fault attacks contained in program code (210). A correction unit (103) makes a correction to the program code (210) to address the vulnerability detected by the detection unit (101). A determination unit (102) determines whether or not vulnerability to fault attacks is present in corrected program code (130) after the correction has been made by the correction unit (103).

This invention discloses a lightweight authentication encryption algorithm differential fault attack method, relating to the fields of cryptography and information security technology; it initializes the AEGIS encryption algorithm and injects a random single-bit fault, with plaintext P as input. i The method involves encrypting the AEGIS encryption algorithm after initialization to generate correct and incorrect ciphertexts and obtaining their output difference. The output difference between the correct and incorrect ciphertexts is then XORed, and the location of the fault is determined using the XOR result. Byte state recovery is then performed based on the XOR result, and the word state recovery process is repeated. Finally, the inverse round function formula and encryption formula are applied to restore the complete internal state. This invention employs a lightweight authentication encryption algorithm differential fault attack method, which can efficiently extract key features from complex high-dimensional time-series data and accurately identify potential fault modes.