11 results about "512-bit" patented technology

The invention discloses a system memory peak bandwidth measurement method and electronic equipment, and relates to the technical field of bandwidth measurement, the memory bandwidth measurement process is optimized through cooperation of dynamic selection of a maximum width vector instruction, forced non-cache access and NUMA perception binding, and the bandwidth measurement efficiency is improved by utilizing the vector processing capacity of a CPU (Central Processing Unit). The data throughput of a single operation is improved to 512 bits or even higher, through cooperation of a non-temporary instruction and a memory barrier instruction, a cache level is bypassed, interference of cache hit or jitter on a measurement result is eliminated, it is ensured that the measurement result truly reflects the performance of a memory system, and the measurement accuracy is improved. Through an automatic NUMA binding mechanism, delay and congestion caused by cross-node access are avoided, and the accuracy, stability and repeatability of a test result are improved.

The invention discloses an authentication encryption method and system with bidirectional linearity. The method comprises the following steps of: (1) jointly selecting an n-bit block cipher E, a secret key K and a block length m by participants; (2) executing an encryption scheme by a sender: calculating an initial state S0 = EK (N) according to a temporary value N; dividing the plaintext M into m bits of blocks M1,..., M1; connecting the Mi with the bit representation of the ordinal number in sequence, inputting a state chain value Si-1 and the Mi [i] n-m into a linear mixing function rho to obtain Si and Ci, and outputting a ciphertext Ci; for the last two blocks Ml-1 and M1, calculating C * for the Ml-1 by using the same method, dividing the C * into Cl-1 and Z, and outputting the Cl-1; and connecting and filling the M1 and the Z, calculating # imgabs0 # and a plaintext length M, calculating # imgabs1 #, and outputting the # imgabs1 #. And (3) the receiver executes the decryption scheme, checks the correctness of the ciphertext and outputs a correctly decrypted plaintext. The method has the implementation advantage of low storage space, the required storage space is close to the block length (32-512 bits) of the block cipher, and the method is suitable for application scenes with limited resources.

The application discloses a data interleaving method and device, and relates to the field of optical fiber communication systems.The method comprises the following steps: dividing an input bit data stream into a plurality of first data blocks by taking 4 bits as a unit, exchanging 2 bits of data in the middle of each first data block; dividing the exchanged bit data stream into second data blocks by taking 512 bits as a unit, and performing intra-block interleaving; and performing inter-block interleaving on the bit data stream after the intra-block interleaving through two random access memories.The application guarantees the original probability distribution characteristics of the PCS technology, and improves the ability of correcting burst errors in the joint application of the FEC technology and the PCS technology.

The invention discloses an acceleration circuit for an SM3 Hash algorithm, which comprises a message filling unit, two message expansion units and two compression iteration units, and is characterized in that the message filling unit fills input data to two times of 512 bits and divides the filled data into a first message block and a second message block; the first message expansion unit calculates a parameter for compressing a first message block and sends the parameter to the first compression iteration unit, and the first compression iteration unit calculates a hash value of the first message block as an initial vector of a second message block and sends the hash value to the second compression iteration unit; the second expansion unit calculates compression parameters for the second message block and sends the compression parameters to the second compression iteration unit, and the second compression iteration unit calculates the hash value of the second message block, namely the hash value of the input data. A sliding window is realized by designing a cyclic shift register group and using 16-stage 32-bit shift registers, and only 16 registers are needed to store an intermediate state, so that storage resources are saved, and the area is optimized.

The present disclosure provides mechanisms to optimize filter processing. Conventional filter processing techniques involve dividing a batch of received data packets into multiple Access Control Lists (ACLs) per filter group, and thus, cannot leverage of optimal ACL processing of large packet batches using the latest processor instruction sets such as 512 bit wide instructions. The filter processing techniques discussed in the present disclosure, some or all rules for a batch of packets are included in a single ACL look-up by including a filter group identifier (ID) in each rule, and also adding the filter group ID to a field of the packet undergoing the ACL look-up. This avoids false matches while also employing a single ACL look-up for an entire batch of packets, regardless of batch-size. The filter processing techniques can be applied to DOCSIS packet processing pipelines and / or other filtering mechanisms.

The application discloses a system memory peak bandwidth measurement method and electronic equipment, and relates to the technical field of bandwidth measurement. The application optimizes a memory bandwidth measurement process by cooperating with a dynamically selected maximum width vector instruction, forced non-cache access and NUMA awareness binding. The application improves single operation data throughput to 512 bits or even higher by using the vector processing capability of a CPU. The application bypasses a cache level by cooperating a non-temporal instruction with a memory barrier instruction, eliminates the interference of cache hits or jitter on measurement results, ensures that measurement results truly reflect the performance of a memory system itself, avoids delay and congestion caused by cross-node access through an automatic NUMA binding mechanism, and improves the accuracy, stability and repeatability of test results.

A CXL module, a control chip, a memory module, and a data transmission method. The CXL module comprises a control chip (100) and a plurality of memory chips (101) connected to the control chip (100) by means of a memory interface of the control chip (100); the control chip (100) is configured to perform ECC coding on data that needs to be stored in the memory chips (101) so as to generate an ECC check code for every 512 bits of data and, on the basis of the memory interface, transmits by means of one burst at least 512 bits of data, the ECC check code of the 512 bits of data, and 2 bits of metadata, wherein the transmission comprises writing data into the memory chips (101) from the control chip (100), or reading data from the memory chips (101) to the control chip (100), and the ECC check code is less than or equal to 30 bits and can correct an error of 1 bit, 2 bits or 3 bits.

The invention relates to the technical field of cryptographic algorithm encryption and decryption, in particular to a cryptographic algorithm encryption and decryption method and system based on a key derivation function, and the method comprises the steps of encrypting a message and decrypting a ciphertext. A key derivation function in the step of encrypting a message and the step of decrypting a ciphertext is accelerated and comprises the following steps of: firstly, executing message expansion and iterative compression of a standard SM3 Hash algorithm on the first 512 bits Z to obtain a 256-bit Hash value H; and then, carrying out batch processing on the remaining 32 bits to obtain a calculation result of the key derivation function. The calculation complexity is reduced through pre-calculation and SIMD instructions, the KDF speed is greatly improved, and the method has the advantages of being universal, small in memory occupation, high in efficiency, safe to achieve and the like.

This invention provides an optimization method for a single 128-entry table based on activation functions. The method accelerates the table lookup logic using SIMD instructions, merges indexes, sets corresponding masks, obtains the correct table entries, and then performs calculations. The method includes: Single-table lookup: Input data is determined to be positive, using only positive entries; Pos_dy: Positive entry 0, a total of 128 entries, each entry is 8 bits, totaling 512 bits, which can be stored in a register; Pos_y0: Positive entry 1, a total of 128 entries, each entry is 8 bits, totaling 512 bits, which can be stored in a register; S1: Input data is cilpped to a threshold range, making it a number between 0 and 127; S2: Original index calculation; S3: Determine the table entry index and use instructions to look up the table; S4: Separate the high and low 4 bits to obtain effective bit width data; S5: Multiply the data obtained from the table entries to obtain the final result. By using SIMD instructions and designing corresponding masks, the table lookup function based on a single 128-entry table based on activation functions is completed.

This invention provides a method for quickly calculating the reciprocal of a positive number based on SIMD instructions, comprising: S1. Loading data, which is loaded in multiples of 32 bits, with a maximum of 512 bits of data per register; single-precision floating-point numbers are 32 bits, and a register can load 16 floating-point numbers, so one SIMD instruction can load or calculate 16 floating-point numbers simultaneously. Let Register1 = Ingenic_simd512_load((float)data); Ingenic_simd512_load is the SIMD instruction for loading data; (float)data is the 16 input 32-bit single-precision floating-point numbers; Register1 is register 1, and the input data is stored in Register1. S2. Use SIMD instructions to calculate the reciprocal of the square root from the data in Register1, and store the result in Register2; S3. Square the reciprocal of the square root from step S2 to obtain the reciprocal. Let Register3 = Ingenic_simd512_float_mul(Register2, Register2); Ingenic_simd512_float_mul is a SIMD instruction for floating-point multiplication. Multiply the data in Register2 with the data in Register2, that is, square the data in Register2, and store the result in Register3; S4. Save the calculation result from the register to memory.

The invention relates to a multi-port primary data caching system supporting concurrent access, and belongs to the technical field of data caching. Through the design of a first-level data cache storage array organization structure, the design of accessing a first-level data cache system by a four-level memory access assembly line to obtain data and the design of an RRIP replacement algorithm, the system data reading delay is delayed by four cycles, the data write-back bandwidth reaches 512b / cycle, concurrent access of three assembly lines is supported, and the data write-back bandwidth reaches 512b / cycle. A high cache hit rate is realized through connection of four paths of groups and an RRIP replacement algorithm, and 128b / 256b vector memory access is supported.