36 results about "512-bit" patented technology

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

The invention discloses a length-configurable vector maximum/minimum network supporting reconfigurable fixed floating points, which comprises a parallel floating point data preprocessing unit, a Mask register, a reconfigurable comparator network and a result selecting unit. The parallel floating point data preprocessing unit is used for analyzing formats of received 512 bit vector data, respectively processing the data according to different data formats, outputting floating point data obtained after processing to the reconfigurable comparator network and outputting various zone bits obtained after processing to the result selecting unit. The Mask register is used for controlling data involved in maximum/minimum. The reconfigurable comparator network is used for inputting the floating point data received from the parallel floating point data preprocessing unit and values received from the Mask register, sequentially comparing the vector data and outputting obtained maximum/minimum results to the result selecting unit. The result selecting unit is used for receiving output of the reconfigurable comparator network and obtaining the final vector maximum/minimum results according to output of the various zone bits received from the parallel floating point data preprocessing unit.

The invention discloses a device compatible with three SHA standards, which comprises a data filling module, a Wt generation module and an Hash operation module, which are connected in order. The invention also discloses a realization method of the device compatible with three SHA standards, which comprises the following steps: (I) receiving cleartext data by the data filling module to generate filling data and outputting the data to the Wt generation module; (II) generating new Wt operators by the Wt generation module and inputting the new Wt operators into the Hash operation module; and (III) generating a data abstract with 160 bits under an SHA-a mode, generating a data abstract with 256 bits under SHA-256 mode or generating a data abstract with 512 bits under an SHA-512 mode by the Hash operation module. The invention has the advantages of common practicality, good compatibility, low power consumption, less occupation of extra resources and the like.

The invention relates to a modified SHA-1 hash algorithm. The existing SHA-1 harsh algorithm has low security. The invention firstly adds a 1, a plurality of 0 and a 64-bit binary string after the information to be processed, then enlarges and groups the information, so the original 512-bit group is changed into a 1024-bit group and a register value is initialized; then a main cycle is utilized to sequentially process each group, the main cycle totally has four operations, and each operation contains logical function and compression function processing; and finally, after the processing of all the groups is completed, 160-bit message digest is output, and when the message digest is transferred, the message to be transferred is added with a safety hashed value. Through the algorithm of the invention, the original SHA-1 algorithm has more safety on message processing, and through modifying the logical function expression and the compression function logical structure of the algorithm, the efficiency of the SHA-1 algorithm is improved.

A method for generating a secure cryptographic hash function supporting 256-512 bit digests is provided. A compression function based on a block cipher in the Davies-Meyer mode is used. A hash function is developed from this compression function using an iterative compression function with the Merkle-Damgård construction, finally resulting in a wide pipe construction in which the intermediate chaining value is at least twice the length of the output hash.

The invention discloses an RSA key pair fast generation system and an RSA key pair fast generation method. The system comprises a CPU core, a cipher coprocessor, a prime number generator, and a memory. The prime number generator is used for filtering composite numbers, is implemented in hardware form, supports 256-bit, 512-bit, 1024-bit, 2048-bit and 4096-bit composite number filtering, and completes modular redundancy, calculation and identification table setting. According to the RSA key pair fast generation method, in order to realize fast key pair retrieving, filtering and judging in an asymmetric algorithm, a hardware-based composite number filtering scheme is adopted, optimized modular exponentiation and improved Montgomery modular multiplication are employed, and the existing prime number decision algorithm is optimized. Thus, efficient prime number screening is realized, the key pair generation speed is increased, and the problem that the generation of an RSA key pair takes long in the existing encryption and decryption technology is solved.

The invention discloses a method for establishing safety communication of network groups. The method comprises the following steps of: processing long-term secret data and authentication information of group communication members by using an SHA (Secure Hash Algorithm) safety hash function which is 512 bits in length; and distributing a key by using an interpolation polynomial according to a secret partition threshold scheme of Shamir to keep a group key fresh, confidential and authenticable and effectively resist external attacks and internal attacks. According to the invention, all information is transmitted on a public channel, so that the method has the characteristics of low calculation amount, high running speed and high server calculation efficiency.

The semiconductor memory device proposed in the present invention comprises memory cells disposed in the row direction and the column direction, a plurality of first lines by which supply voltages are supplied in order to select memory cells disposed in the row direction among the plurality of cells, a plurality of second lines by which supply voltages are supplied in order to select memory cells disposed in the column direction among the plurality of cells, the data lines which input and output the data to the selected memory cells, the first power voltage supply circuit which supplies the predetermined supply voltages to the first lines corresponding with the externally input row address synchronizing with an act command, and the second power voltage supply circuit which supplies the predetermined supply voltages to the second lines corresponding with the externally input column address synchronizing with an act command. It also comprises m pieces of memory banks (m is a natural number larger than 2) which write or read the data into or from the memory cells which are selected one after another in the row or column directions, data input circuits in which multiple bits of serial data which is larger than 512 bits to be written in the m pieces of memory banks, data output circuits which reads the data from the m pieces of memory banks and output in a form of multiple bits of serial data which is larger than 512 bits, and data conversion circuits which convert the serial data input in the data input circuits to parallel data so that it can be written in each memory bank or to convert each parallel data read from each memory bank to serial data so that such data are supplied to the data output circuits.

The invention discloses an ultrahigh-throughput MD5 brute-force cracking device implemented based on a FPGA (Field Programmable Gate Array) in the technical field of digital information processing. The ultrahigh-throughput MD5 brute-force cracking device comprises an input interface module, a raw data generation module, a MD5 computation module and an output module implemented in the FPGA, and a keyboard input device and a display interface device connected to the FPGA; the input interface module is connected with the keyboard input device and transmits a target MD5 value and control computation information input by a user, the raw data generation module is connected with the input interface module and the MD5 computation module and transmits 512-bit raw data block information to the MD5 computation module under the control of a clock signal, the MD5 computation module is connected with the input interface module, the raw data generation module and the output interface module and transmits computation result to the output interface module, and the output interface module is connected with the display interface device and transmits the computed target MD5 value and the computation result. In the ultrahigh-throughput MD5 brute-force cracking device implemented based on the FPGA, information is stored in a FIFO (First in First out) memory so as to cooperate with the computation of the whole pipeline architecture, and computation efficiency is improved.

The invention provides a high-throughput SHA-1 (Secure Hash Algorithm) based on an FPGA. The method comprises the steps of S1, judging whether length of input message data exceeds 512 bits or not; S2, carrying out bit compensation on the message data until the length is integer multiples of the 512 bits if the length of input message data exceeds 512 bits; S3, segmenting the message data after bit compensation into multiple data blocks, wherein each data block is 512 bits, and segmenting each data block into 16 characters, wherein each character is 32 bits; S4, carrying out loop unrolling on an original iteration operation formula, thereby forming a loop unrolling structure; S5, determining pipeline series, and forming a pipeline structure by an intermediate register and the loop unrolling structure; and S6, inputting each character into the pipeline structure, thereby obtaining a SHA-1 calculation result. According to the algorithm, the iteration operation is simplified, an intermediate variable is added, therefore, a key path is shortened, and a calculation speed is improved. Moreover, through adoption of a pipeline processing mode, the data processing quantity is increased, and the throughput is improved.

A method of new radio physical broadcast channel (NR-PBCH) bit mapping is proposed to improve for NR-PBCH decoding performance under Polar codes. NR-PBCH carries 32 information bits and 24 CRC bits. Specifically, NR-PBCH uses 512-bit Polar codes to carry total 56 data bits. Different Polar code bit channels have different channel reliability. As a general rule, the most reliable Polar code bit channels are used for the 56 data bits. In accordance with a novel aspect, within the 32 NR-PBCH information bits, some of the information bits that can be known to the decoders under certain conditionsand therefore are placed at the least reliable Polar code bit positions. As a result, by mapping the NR-PBCH data bits properly at the input bit positions of Polar codes, the NR-PBCH decoding performance is improved when the known bits a priori can be exploited.

The invention provides a message expansion circuit in a low-power-consumption SHA256 algorithm, and belongs to the technical field of digital integrated circuits. The problem that a message expansioncircuit in an SHA256 circuit is too high in power consumption is solved. The technical scheme is as follows: the circuit comprises a message expansion circuit in a low-power-consumption SHA256 algorithm. The message expansion circuit comprises a group of 512-bit message and shift multiplexing registers M, four groups of three-state gates Gate1, Gate2, Gate3 and Gate4, a group of operational logiccircuits and a group of 6-bit comparators P1. The beneficial effects of the invention are that the comparator and the three-state gate turn-off operation circuit are used for input, thereby saving thepower consumption, and achieving the purpose of saving the power consumption.

A method of completing the Secure Hash Algorithm (SHA-1) computation in exactly 81 clock cycles with digital hardware. The general implementation techniques include: using a combination of synchronous storage elements to store the required computation values and asynchronous circuits to perform all the logic and mathematic operations of each step of the 81-step SHA-1 computation within a single clock cycle; using a quad-output-channel 16×32-bit circular queue memory to store the 512-bit message segment (block), as a computation buffer of the Wt parameter, and to supply the Wt-3, Wt-8, Wt-14, and Wt-16 data parameters simultaneously; using a combination of a counter circuit and a decoder/encoder circuit to control selecting data parameters and sequencing the 81-step SHA-1 computation; and using an automated controller to control internal units that perform SHA-1 and allowing external systems to access the SHA-1 computation service. The robust architecture allows for a highly efficient digital hardware implementation.

The invention provides a selective satellite image compression encryption method based on Chacha20 and CCSDS. Aiming the characteristics of a satellite image, the method comprises the steps: firstly carrying out the three-stage two-dimensional discrete wavelet transformation through employing a 9/7 integral wavelet in a CCSDS image compression algorithm, and obtaining a DC coefficient and an AC coefficient after transformation; secondly generating a ChaCha20 initial byte stream through the head information in a coding item and a 512-bit initial secret key and ChaCha20 Hash; thirdly carrying out the summation and modular operation of a chaos initial secret key and a plaintext image normalization value through the byte stream generated by PWLCM (Piecewise Linear Chaotic Map) and the ChaCha20 initial byte stream, and generating a ChaCha20 byte stream; fourthly carrying out the XOR encryption of the ChaCha20 byte stream and the DC coefficient and AC coefficient (the father and son coefficients in each block) and all AC coefficient symbol bites; finally enabling the encrypted DC and AC coefficients to be coded and compressed, and completing the compression and encryption of the satellite image. The generation of the ChaCha20 byte stream is related with the to-be-encrypted satellite image and a compression coding parameter, thereby improving the encryption adaptability.

The invention provides a BMC-based random number generation method and system. The method comprises: S1, generating system current time value data by using a real-time clock module; S2, transmitting the current time value data to an SM3 algorithm module, supplementing 0 at a high position of the time value data through the SM3 algorithm module, and enabling the time value data to reach 512 bits; and S3, carrying out operation on 512-bit clock data per second to generate a 256-bit hash value, and taking the hash value as a random number. According to the method and the system, a random number generation function is realized through a software mode. The system current time value data generated per second by the real-time clock module is transmitted to the SM3 algorithm module. The SM3 algorithm module generates a 32-byte hash value per second as a random number, so that generation of random number is realized, and requirement of using random number by BMC is effectively met. According tothe technical scheme, the generated random number is high in stability, hardware resources of a server mainboard is not occupied, and the system is free of additional cost and is high in operability,and the design flexibility is improved.

The invention, which belongs to the technical field of chip circuit design, discloses an amplitude-phase precision adjustable attenuation phase shift architecture comprising an active numerical control attenuator, an active numerical control phase shifter, and a table look-up code value register. According to the invention, under the background that an external system requires 6-bit attenuation and 6-bit phase shift, the direct attenuation bit number and the phase shift bit number are respectively increased to 9 bits, so that further improvement of the amplitude-phase precision becomes possible; in addition, based on the architecture, under the condition that the system complexity and the write-in data time of the power-on table look-up code value register are allowed, the 9-bit direct control bit can still be further increased; along with the increase of direct control bits, corresponding attenuation and phase shift phases are respectively increased to 512 bits from original 64 bits, and each attenuation state and each phase shift state can be selected from a plurality of states under the condition that external 6-bit control bits are not changed. Different code values can be written into a table look-up code value register to realize on-chip adjustment and optimization of an amplitude-phase multifunctional chip according to index requirements of different attenuation phase shift precisions of a system.

The invention discloses a rapid Montgomery modular multiplier optimization component suitable for a national cryptographic sm2p256v1 algorithm. The component includes a large number multiplier, a temporary variable producer, a cyclic carry accumulator and a large number subtracter. A large integer A and a large integer B with the bit width of 256 bit are input and processed by the large number multiplier to obtain a large integer Z with the bit width of 512 bit. Temporary variables X1 and X2 are generated through Z, and then the temporary variables X1 and X2 and Z are subjected to carry accumulation operation for eight times. A result Z obtained by carry accumulation of each time is used as an input of the carry accumulator and the temporary variable generator, if Z is greater than or equal to a large integer constant M after eight carry accumulation operations are completed, a large number subtraction operation is performed on M and Z once, otherwise, directly a result of eight timesof the cyclic carry accumulator is output.