Length-configurable vector maximum/minimum network supporting reconfigurable fixed floating points

Abstract

The invention discloses a length-configurable vector maximum / minimum network supporting reconfigurable fixed floating points, which comprises a parallel floating point data preprocessing unit, a Mask register, a reconfigurable comparator network and a result selecting unit. The parallel floating point data preprocessing unit is used for analyzing formats of received 512 bit vector data, respectively processing the data according to different data formats, outputting floating point data obtained after processing to the reconfigurable comparator network and outputting various zone bits obtained after processing to the result selecting unit. The Mask register is used for controlling data involved in maximum / minimum. The reconfigurable comparator network is used for inputting the floating point data received from the parallel floating point data preprocessing unit and values received from the Mask register, sequentially comparing the vector data and outputting obtained maximum / minimum results to the result selecting unit. The result selecting unit is used for receiving output of the reconfigurable comparator network and obtaining the final vector maximum / minimum results according to output of the various zone bits received from the parallel floating point data preprocessing unit.

Description

technical field [0001] The invention relates to the technical field of high-performance digital signal processors, in particular to a reconfigurable length-configurable vector maximum / minimum network supporting fixed-floating points. Background technique [0002] With the rapid development of computer and information science, digital signal processor (DSP) technology came into being. In the past 40 years, DSP has been developed by leaps and bounds. In DSP, no matter how complicated the operation is, it is finally implemented by the operation unit. Therefore, the operation unit is the core component of the entire DSP. In recent years, with the continuous development of the field of digital signal processing, the application of DSP has promoted the development of DSP, and the DSP for specific fields and specific needs is the direction of its continuous development. [0003] There are a large number of maximum / minimum value operations in the field of digital signal processing,...

AI Technical Summary

Problems solved by technology

Taking the ADITS20XS series DSP as an example, although a 32-bit fixed-point data can be configured as 1 / 2 / 4 32 / 16 / 8-bit fixed-point data, and supports 8 / 16 / 32-bit fixed-point data format, it is in the 8 / 16-bit In the mode, the maximum / minimum value can only be taken from the corresponding two data in turn, instead of taking from 8 / 4 8 / 16 bits (2 32-bit fixed points can be configured as 8 8-bit, 4 16-bit) max / min

[0006] 3) The number of data is not configurable

Some existing patents and literature have optimized the maximum / minimum value operations, but they are only limited to the level of scalar processor multiplexed ALU, and the fixed and floating-point maximum / minimum value operations are completely separated, and there is no further research Max / min network unique to vector processors

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