9 results about "Loop unrolling" patented technology

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a fusion engine. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU detects a loop body ME within the program instruction stream, accumulates loop iteration count information about a series of instances of a loop on the loop body ME in the program instruction stream, updates a consistency counter of the loop body ME while accumulating the loop iteration count information, and in response to detecting that the consistency counter has reached a threshold, instructs the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is a loop unroll factor that is at least two.

A microprocessor includes a prediction unit (PRU) comprising a fetch block (FBlk) predictor (FBP) that predicts a sequence of FBlks, each FBlk having a corresponding fetch block start address (FBSA), and branch predictors; a macro-op (MOP) cache (MOC) includes MOC entries (MEs) including multi-FBlk MOC entries (MF-MEs) for holding MOPs decoded from instructions of multiple FBlks. The PRU detects a hit of a current FBSA on an MF-ME; performs a set of actions K times: looking up the current FBSA in the FBP and branch predictors to obtain outputs, using the outputs to predict a successor FBSA of a successor FBlk; and making the current FBSA the successor FBSA; and predicts that an FBSA of a successor FBlk to the MF-ME is the current FBSA resulting from performing K times the set of actions. K is a number of FBlks built into the MF-ME (alternatively times a loop unroll factor).

Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

The present application relates to the technical field of neural network optimization, and more particularly to a dynamic cross-layer data multiplexing method for efficient deep convolution calculation, comprising: step 1, designing a single-layer block optimization and loop sequence optimization model; step 2, performing separate block optimization and loop sequence optimization; step 3, performing multi-layer joint block optimization and loop sequence optimization; and step 4, performing dynamic composite block optimization and loop sequence optimization of single-layer and multi-layer. The present application can finally realize a multi-layer joint data block strategy with minimum DRAM access, a loop unrolling control strategy, and a data storage mapping update strategy, and realize a data access and data flow scheme with maximized data multiplexing of fine granularity, which can effectively support code automatic generation and calculation mapping optimization for optimizing calculation and memory efficiency.

The invention discloses a vectorization method for a homomorphic encryption compiler, and the method comprises the following steps: S1, obtaining a cloud homomorphic encryption calculation-oriented source program written by a developer; s2, converting a source program into an intermediate representation, and executing loop expansion optimization on the intermediate representation to obtain a scalar intermediate representation without control flow; s3, converting the scalar intermediate representation into a directed acyclic graph G (V, E); s4, calculating the ASAP and ALAP attribute of each node in the directed acyclic graph, and determining the maximum lane width required by the directed acyclic graph; s5, constructing an integer linear programming model based on the parameters; and S6, solving the integer linear programming model, and generating a vectorized homomorphic encryption program according to a solving result and a homomorphic encryption library at the rear end of the target hardware. According to the method, manual intervention is not needed, regular and irregular programs are supported, the speed is averagely increased by 5.95 times at the CPU end and 3.79 times at the GPU end compared with a scalar program, and the homomorphic encryption technology is assisted.

The invention discloses a multi-heterogeneous main body system optimization method and system oriented to a real-time processing scene, and the method comprises the steps: a CPU employs a bare core BMP mode for parallel division of labor, the CPU comprises a plurality of large cores and a plurality of small cores, a control task and a protection task are operated on the large cores, a master station command is received, and a background task is operated on the small cores; the FPGA writes back and reads data between a DDR (Double Data Rate) memory of the CPU and an internal cache of the FPGA according to a set time slot or period, and data preprocessing carried out in the data writing back and reading process is migrated from the CPU to an FPGA layer to be executed; three-buffer independent access and atomic state switching are combined, and data interaction among multiple cores is carried out; the compiler automatically inserts a prefetch instruction in a loop expansion and pipeline scheduling stage; and the compiler performs linear address arrangement on the data members in a physical address space. The instruction execution efficiency and the data access efficiency are improved.

A loop vectorization method and apparatus are disclosed. The loop vectorization method includes: in response to determining that the current loop can be rolled back, creating a first data structure corresponding to the current loop after the loop rollback; for the current loop and the first data structure, determining the maximum vectorization factor and candidate vectorization factors of the current loop that will not cause register overflow, respectively; determining the optimal vectorization factor from the candidate vectorization factors; in response that the optimal vectorization factor is a candidate vectorization factor determined for the first data structure, performing a loop rollback on the current loop to reduce the number of registers used in each iteration of the current loop after the loop rollback; selectively performing loop unrolling on the current loop after the loop rollback to obtain a first target loop; and performing a vectorization transformation on the first target loop based on the optimal vectorization factor.

An information processing apparatus that generates an operation configuration including functional units to be used, a connection path between the functional units, and an output path of an operation result, for a reduction operation, based on a plurality of pieces of operation input data including sets of two pieces of data, the information processing apparatus comprising, a memory, and a processor coupled to the memory and configured to, generate an initial operation configuration based on a loop unrolling factor that is a number of the functional units that perform the predetermined operation with the operation input data as a direct input, and generate a first operation configuration by adding an output path of an operation result for a different degree of parallelism in a case where the predetermined operation is repeated with a predetermined degree of parallelism to the generated initial operation configuration.

The invention relates to the technical field of automatic tuning of Triton compilers, and discloses an automatic tuning method for improving heterogeneous parallel computing performance, which comprises the following steps of: constructing a parameter space containing thread quantity, circular pipeline depth, data block size, register use quantity limitation and circular expansion factors; a variational automatic encoder is utilized to encode historical optimization data, the dependency relationship among parameters is learned, and joint probability distribution of a parameter space is generated. The combination of a Triton compiler and machine learning is realized for the first time, an optimal parameter combination is selected from rich configurations, the compiling overhead is reduced, the reasoning efficiency of a front-end model is improved, the energy consumption of a parallel system is saved, and the prediction precision, the balance performance and the energy efficiency are continuously improved through iterative optimization. The problem that parallel parameters cannot be combined with application programs and hardware feature information to make optimal solutions is solved.