46 results about "Loop unrolling" patented technology

The invention is directed to data receivers such as those used in semiconductor devices. Embodiments of the invention provide a loop unrolling DFE receiver that uses analog control signals from each equalizer to avoid timing delays associated with the use of latched digital control signals in the conventional art. In addition, embodiments of the invention implement each equalizer with a single sense amplifier based flip flop (SAFF) to reduce circuit size and power consumption

The invention provides a high-speed accurate single-pattern character string matching method, comprising a pretreatment phase and a search phase; wherein, the pretreatment phase comprises three main steps: pretreating patterns, pretreating texts and judging optimal matching action in accordance with matching conditions; the search phase is a process of string matching and comprises three main steps: Scan Loop, Match Loop and subsequent judgment action. In the invention, the following improvements are made on the basis of an SBNDM2 algorithm, one of the top-speed methods when matching is carried out in current corpora of English: reducing the expenditure of index bound detection by introducing an index bound protection mechanism; simplifying the algorithm by the way of modifying the definitions of bitmasks and bit vectors; determining a method for selecting the optimal loop unrolling characters with regard to different pattern lengths and different corpora by expanding the loop unrolling mechanism of SBNDM2 and improving the matching performance of the algorithm aiming at different matching conditions. The method of the invention is a high-speed bit parallel accurate single-pattern string matching method with high performance and broad application range when the pattern length is not more than the machine word-length.

A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

The invention discloses a runtime error analytical method based on abstract interpretation and model verification. The method includes the following steps that on the basis of the abstract interpretation theory, the program numerical variable value range is analyzed by the adoption of a forward iteration method, the variable value range information is obtained when program points are stable, and the iterative computations of loop nodes are achieved by the way that loop unrolling and delay widening are combined; the variable value range information at the relevant program points needing to be detected is converted to be in an assertion or hypothesis mode to be plugged into a program according to a runtime error type to be analyzed; the assertion or hypothesis programs are converted into a Boolean formula, wherein the Boolean formula comprises limiting conditions and attributes; the correctness of the attributes in the Boolean formula is judged through an SAT verifier, if correct, it shows that relevant runtime errors do not exist, if not correct, it shows that the relevant runtime errors exist, and relevant counter example paths are output. By means of the method, an equilibrium point is acquired between runtime error analysis precision and efficiency.

The invention puts forward a high-performance realization method of a BLAS (Basic Linear Algebra Subprograms) three-level function GEMM on the basis of an SW platform. An ''interface-driver-kernel assembly core code'' three-layer code design framework is adopted by aiming at a domestic SW1600 platform, technical means, including a multiply-add instruction, loop unrolling, software pipeline instruction rearrangement, SIMD (Single Instruction Multiple Data) vector operation, register blocking technology and the like which are associated with platform architecture, are adopted to realize assembly level manual optimization, the problem that a compiler can not sufficiently optimize a compute-intensive function GEMM is solved, and function performance is greatly improved. Compared with an open source BLAS math library GotoBLAS, the high-performance realization method is characterized in that an average speed-up ratio is 4.72 and a highest speed-up ratio is 5.61.

Agile BCH encoders are useful when the noise characteristics of the channel change which demands that the strength of the error correcting BCH code to be a variable. An agile encoder for encoding a linear cyclic code such as a BCH code, is a code that switches code strength (depth) relatively quickly in unit increments. The generator polynomial for the BCH code is provided in the factored form. The number of factored polynomials (minimal polynomials) chosen by the system determines the strength of the BCH code. The strength can vary from a weak code to a strong code in unit increments without a penalty on storage requirements for storing the factored polynomials. The BCH codeword is formed by a dividing network and a combining network. Special method is described that provides a trade off mechanism between latency and throughput while simultaneously optimizing the delay in the critical path which is in the forward path. Speed enhancements at minimal polynomial level are also provided by retiming, loop unfolding, loop unrolling, and special mathematical transformations. The presented invention can be implemented as an apparatus using software or hardware or in integrated circuit form.

The invention belongs to the technical field of high-performance calculation, and relates to a method for optimizing a finite difference algorithm in a heterogeneous many-core framework. The method is used for optimizing the finite difference algorithm in a many-core accelerator (MIC) and multi-core general processor (CPU)-based hybrid heterogeneous high-performance computer system by using three progressive optimization methods. The method mainly comprises a basic optimization method, a parallel optimization method and a heterogeneous collaborative optimization method. The method disclosed in the invention has the beneficial effects as follows: the three progressive optimization methods are used for solving the problems of low calculation performance and bad parallel effect caused by leap-type access and parallel execution lack when converting the finite difference algorithm from a many-core system to a heterogeneous many-core; the method is an optimization method with high efficiency and expandability, and can be used for weakening the calculation strength and clearing obstacles for vectorization through basic optimization methods such as branch elimination, loop unrolling and invariant switching; and the parallel optimization method such as a core algorithm is rewritten by using a vector instruction set through analyzing data dependency and circulating partitioning, and a multi-threading and long-vector mechanism of the many-core processor is fully utilized.

The invention discloses a circulating-unfolded-structured AES encryption/decryption circuit based on a data redundancy real-time error detection mechanism, and is used for resisting fault injection attacks or used for improving circuit reliability in an extreme application environment. The circuit comprises two parts of an AES encryption/decryption unit and a detecting unit, wherein the AES encryption/decryption unit adopts the circulating-unfolded structure, and is formed by Nk round transformation units and an alternative selector; the detecting unit is composed of Nk comparators. The AES encryption/decryption unit adopts the data redundancy processing technology in the data processing process, utilizes two adjacent round transformation units to perform the same operation on each group of data twice; the comparators in the detecting unit compare the results of the two operations; the AES encryption/decryption unit works normally if the operation results are the same; the AES encryption/decryption unit generates an error if the results are different. Compared with the conventional structural redundancy error detection mechanism, the adoption of data redundancy error detection mechanism can greatly reduce the circuit area.

The invention discloses a complex matrix optimizing method, which is characterized by comprising the steps: firstly calculating the specific unrolling granularity of the godson architecture, carrying out four-by-four loop unrolling to a complex matrix, and selecting a maximum value as the size nb of a partitioning block of a matrix so as to obtain the optimal ideal size of the partitioning block of the matrix on the godson, wherein the maximum value of the size nb of the partitioning block of the matrix is smaller than 52, and the product of 24 and the square of the size nb of the partitioning block of the matrix is smaller than the maximum of 64 kilobyte of a first data cache of a godson processor; reasonably dividing and combing matrixes in a matrix multiplication by utilizing the continuity and the locality of data storage, and reducing the cache access number of the first grade data of the godson; and carrying out the common complex addition and multiplication in the complex matrix operation by utilizing the multiplication of two complexes in the classic complex algorithm so as to reduce the operating scale, so that the calculation performance of the complex matrix multiplication on the godson is enhanced by about 50%, and the operating rate of BLAS (basic linear algebra subprograms) base on the godson 3A is increased by more than 1.5 times.

The invention relates to a compilation method and a compiler. The compilation method comprises: identifying a cycle containing first instructions, in which, the cycle has a definite control parameter and does not contain transfer instructions, and all first instructions do not have iterative correlation; compiling statistics of the number of the first instructions and second instructions in the cycle, and calculating cycle unfolding frequency and the cycle frequency of converting the first instructions into the second instructions according to the executing capability of a first instruction executing part and a second instruction executing part; carrying out cycle unfolding for the cycle when the cycle unfolding frequency is not equal to one, and converting the first instructions in the cycle unfolding into the corresponding second instructions according to the cycle frequency of converting the first instructions into the second instructions. The compilation method and the compiler can make full use of the parallelism of instruction executing parts in a processor to increase program executing efficiency and reduce the programming burden of a user.

The invention provides a high-throughput SHA-1 (Secure Hash Algorithm) based on an FPGA. The method comprises the steps of S1, judging whether length of input message data exceeds 512 bits or not; S2, carrying out bit compensation on the message data until the length is integer multiples of the 512 bits if the length of input message data exceeds 512 bits; S3, segmenting the message data after bit compensation into multiple data blocks, wherein each data block is 512 bits, and segmenting each data block into 16 characters, wherein each character is 32 bits; S4, carrying out loop unrolling on an original iteration operation formula, thereby forming a loop unrolling structure; S5, determining pipeline series, and forming a pipeline structure by an intermediate register and the loop unrolling structure; and S6, inputting each character into the pipeline structure, thereby obtaining a SHA-1 calculation result. According to the algorithm, the iteration operation is simplified, an intermediate variable is added, therefore, a key path is shortened, and a calculation speed is improved. Moreover, through adoption of a pipeline processing mode, the data processing quantity is increased, and the throughput is improved.

The invention provides a multi-rate multi-code length LDPC code decoding method based on a SIMD instruction set. The method comprises the following steps: realizing check matrix information online statistic through external configuration document by combining the LDPC code-based matrix feature in quasi-cyclic structure; through the adoption of a fixed point layered decoding scheme, respectively constructing a specific check node computing unit for different row weights by a decoder, and selecting the check node computing unit according to different row weights, wherein a cyclic expansion way is adopted in the check node computing unit. The online statistic of the check matrix information is realized, and the storage amount of the multi-rate multi-code length LDPC code decoder is reduced; compared with the existing algorithm, the dependence on the matrix statistical information is eliminated, and the realization complexity of the decoder is realized; compared with the existing algorithm, the speed loss is avoided, and the module for online computing can be modified, and the universality is provided.

A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

The invention provides a data processing method, apparatus and device, and a computer storage medium. The method comprises the steps of obtaining an intermediate representation of a deep learning model; wherein the loop expansion factor is related to information of the intermediate representation during execution of the rear-end hardware equipment and/or equipment information of the rear-end hardware equipment; performing loop expansion on the intermediate representation according to the loop expansion factor to obtain an optimized intermediate representation; and compiling the optimized intermediate representation to obtain a target code which can be executed by the back-end hardware equipment, so that the back-end hardware equipment executes the target code to realize the function of the target code. By adopting the embodiment of the invention, the loop expansion factor can be calculated according to the execution information of the rear-end hardware equipment and/or the equipment information of the rear-end hardware equipment to obtain a more accurate loop expansion factor, and the intermediate representation is subjected to loop expansion through the loop expansion factor, so that instruction scheduling is carried out in a larger range; and the transportability of the intermediate representation is improved.

A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators in the DFE receiver; utilizing the comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively. The method and the apparatus can adaptively adjust equalization information input to the comparators in the receiver such as the DFE receiver.

A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.