46 results about "Loop unrolling" patented technology

A profile-based loop optimizer generates an execution frequency table for each loop that gives more detailed profile data that allows making a more intelligent decision regarding if and how to optimize each loop in the computer program. The execution frequency table contains entries that correlate a number of times a loop is executed each time the loop is entered with a count of the occurrences of each number during the execution of an instrumented instruction stream. The execution frequency table is used to determine whether there is one dominant mode that appears in the profile data, and if so, optimizes the loop according to the dominant mode. The optimizer may perform optimizations by peeling a loop, by unrolling a loop, and by performing both peeling and unrolling on a loop according to the profile data in the execution frequency table for the loop. In this manner the execution time of the resulting code is minimized according to the detailed profile data in the execution frequency tables, resulting in a computer program with loops that are more fully optimized.

The invention is directed to data receivers such as those used in semiconductor devices. Embodiments of the invention provide a loop unrolling DFE receiver that uses analog control signals from each equalizer to avoid timing delays associated with the use of latched digital control signals in the conventional art. In addition, embodiments of the invention implement each equalizer with a single sense amplifier based flip flop (SAFF) to reduce circuit size and power consumption.

Methods and apparatus are disclosed for improved loop unrolling by a compiler. A large class of loops exists for which effective loop unrolling has not previously been performed because they are too large to be completely unrolled, but which do not have a single hot trace that covers an entire loop iteration. The present invention recognizes such loops that have partial hot traces identified using profile data. A set of instructions which constitute a proper superset of the hot trace and a proper subset of the entire loop, and which forms a complete loop iteration is identified. This set of instructions can then be unrolled without unrolling the entire loop.

An apparatus and a method for processing an array in a loop in a computer system, including: applying loop unrolling to a multi-dimensional array included in a loop based on a predetermined unrolling factor to generate a plurality of unrolled multi-dimensional arrays; and transforming each of the plurality of unrolled multi-dimensional arrays into a one-dimensional array having an array subscript expression in a form of an affine function with respect to a loop counter variable.

The invention relates to a fixed-temperature command-level self-test method for detecting time-delay faults in an internal temperature rise mode. The high-temperature time-delay test is performed on a processor, comprising the following steps: obtaining the original command-level self-test program module; and performing the original command-level self-test program module Carry out the deformation of loop unrolling; carry out the deformation of the original instruction level self-test program module based on triggering cache miss; within the set test temperature range, use the fixed temperature test program scheduling algorithm to obtain feasible scheduling; heat the processor to the test temperature range The lower bound of , according to the feasible schedule, execute the corresponding program, and implement the constant temperature test of internal heating for delay faults. Compared with the prior art, the invention has the advantages of being able to effectively test delay faults under high temperature conditions, ensuring high fault coverage, reducing processor loss and the like.

The invention discloses a method for reducing register overflow caused by fine-grained randomization safety optimization, and relates to the technical field of compiler cycle optimization. First, the variables in the registers in the cycle body are reclassified, including cycle invariants, cycle induction variables and cycle changes. After the classification, the variables in the registers in the loop body are identified; finally, according to the number of loop invariants, loop induction variables, and loop variations in the loop body registers after identification, the loop expansion factor is obtained. The present invention proposes register pressure sensitive The loop unrolling method can improve the loop optimization effect to a certain extent and reduce the occurrence of register overflow; in addition, for randomization optimization, hot code, generally the loop body is more sensitive to the performance load brought by randomization, thus improving loop unrolling Optimizations can also improve the performance of fine-grained randomization security optimizations.

The invention discloses a circulating-unfolded-structured AES encryption / decryption circuit based on a data redundancy real-time error detection mechanism, and is used for resisting fault injection attacks or used for improving circuit reliability in an extreme application environment. The circuit comprises two parts of an AES encryption / decryption unit and a detecting unit, wherein the AES encryption / decryption unit adopts the circulating-unfolded structure, and is formed by Nk round transformation units and an alternative selector; the detecting unit is composed of Nk comparators. The AES encryption / decryption unit adopts the data redundancy processing technology in the data processing process, utilizes two adjacent round transformation units to perform the same operation on each group of data twice; the comparators in the detecting unit compare the results of the two operations; the AES encryption / decryption unit works normally if the operation results are the same; the AES encryption / decryption unit generates an error if the results are different. Compared with the conventional structural redundancy error detection mechanism, the adoption of data redundancy error detection mechanism can greatly reduce the circuit area.