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3 results about "Loop unrolling" patented technology

Loop unrolling, also known as loop unwinding, is a loop transformation technique that attempts to optimize a program's execution speed at the expense of its binary size, which is an approach known as space–time tradeoff. The transformation can be undertaken manually by the programmer or by an optimizing compiler.

Integrating loop unrolling and loop splitting to reduce control overheads

ActiveUS12632233B2Code compilationControl flowLoop splitting
Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.
Owner:INTERNATIONAL BUSINESS MACHINE CORPORATION

Multi-heterogeneous main body system optimization method and system oriented to real-time processing scene

The invention discloses a multi-heterogeneous main body system optimization method and system oriented to a real-time processing scene, and the method comprises the steps: a CPU employs a bare core BMP mode for parallel division of labor, the CPU comprises a plurality of large cores and a plurality of small cores, a control task and a protection task are operated on the large cores, a master station command is received, and a background task is operated on the small cores; the FPGA writes back and reads data between a DDR (Double Data Rate) memory of the CPU and an internal cache of the FPGA according to a set time slot or period, and data preprocessing carried out in the data writing back and reading process is migrated from the CPU to an FPGA layer to be executed; three-buffer independent access and atomic state switching are combined, and data interaction among multiple cores is carried out; the compiler automatically inserts a prefetch instruction in a loop expansion and pipeline scheduling stage; and the compiler performs linear address arrangement on the data members in a physical address space. The instruction execution efficiency and the data access efficiency are improved.
Owner:BEIJING SIFANG JIBAO ENG TECH +1

Cyclic vectorization method and apparatus

PendingCN122285004Areduce in quantityReduce risk of spillageAlgorithmControl theory
A loop vectorization method and apparatus are disclosed. The loop vectorization method includes: in response to determining that the current loop can be rolled back, creating a first data structure corresponding to the current loop after the loop rollback; for the current loop and the first data structure, determining the maximum vectorization factor and candidate vectorization factors of the current loop that will not cause register overflow, respectively; determining the optimal vectorization factor from the candidate vectorization factors; in response that the optimal vectorization factor is a candidate vectorization factor determined for the first data structure, performing a loop rollback on the current loop to reduce the number of registers used in each iteration of the current loop after the loop rollback; selectively performing loop unrolling on the current loop after the loop rollback to obtain a first target loop; and performing a vectorization transformation on the first target loop based on the optimal vectorization factor.
Owner:SAMSUNG (CHINA) SEMICONDUCTOR CO LTD +1