76 results about "Matrix partitioning" patented technology

An expense allocation method utilizes matrix multiplication to transform a set of reciprocal or cascading allocation rules into a new set of one-step allocation rules. The new set of rules reallocates amounts directly to the ultimate destination without going through numerous intermediate levels of reallocation. By taking advantage of the specific structure of the matrix, and partitioning the matrix into four (4) subparts, the matrix multiplication process is greatly simplified. The expense allocation method can be easily and efficiently implemented on a computer system, including computers based upon parallel or vector architectures. This invention permits most allocation work to be done before the end of an accounting period, allowing end-of-period accounting work to be completed sooner. Alternatively, expenses can be allocated as they occur, rather than waiting until the end of a period.

A method for forming a plurality of parity check matrices for a plurality of data rates for use in a Low-Density Parity-Check (LDPC) decoder, comprises establishing a first companion exponent matrix corresponding to a first parity check matrix for a first data rate, and partitioning the first parity check matrix and the first companion exponent matrix into sub-matrices such that the first parity check matrix is defined using a cyclical shift of an identity matrix.

One embodiment of the device includes a display panel and a light source evenly placed behind the panel, wherein the light source includes light source blocks divided and arranged in a matrix, includes an image judging unit which divides one frame of a video input signal into frame blocks each corresponding to a size of each of the light source blocks and judging whether images of the frame blocks are moving or still, and a light source block driving unit which blinks the light source block corresponding to the frame block the image of which is judged as moving by the judging unit upon receiving optical responses from the cells while turning on all the time the light source block corresponding to the frame block the image of which is judged as still by the judging unit.

The present invention relates to a method of simulating the deformation of a viscoelastic material in which filler is blended to a matrix made of rubber or resin, the method including the steps of dividing the viscoelastic material into a finite number of elements to form a viscoelastic material model, a step of performing deformation calculation of the viscoelastic material model based on a predetermined condition, and a step of acquiring a necessary physical amount from the deformation calculation, where the step of dividing the viscoelastic material into a finite number of elements includes a step of dividing at least one filler into a finite number of elements to form a filler model, and a step of dividing the matrix into a finite number of elements to form a matrix model.

The invention relates to a privacy protection associated rule data digging method based on multi-parameter interference. The method includes: building an original data set into a two-dimensional Boolean matrix D, using data interference and inquiry limiting strategies to performing random interference on the Boolean matrix D so as to increased privacy protection degree and obtain the interfered data set D'; using the modified MASK algorithm to perform item set support degree reconstruction on the interfered data set D', and optimizing the counting process through a set principle to obtain a frequent item set and associated rules. Compared with the prior art, the method has the advantages that data interference strategy are combined with inquiry limiting strategy, the defects of each of the data interference strategy and the inquiry limiting strategy are overcome, and privacy protection degree is increased; the recurrence relation between probability inverse matrixes is discovered according to the matrix partitioning thought, the complex process which requires that the probability matrixes need to be solved before the inverse matrixes are calculated, the counting process is optimized on the basis of the set principle, exponential order time complexity during the counting process is eliminated, and the execution efficiency of the method is increased greatly.

The invention discloses a method for testing motion available for real-time monitoring. Based on the analysis theory of an independent vector, a motion foreground and an environment background are taken as the main composition of a whole image; and corresponding data fusion is carried out on two observation vectors, and a mixing relationship between the vectors which are mutually independent in the statistical sense is adjusted so as to lead the motion foreground and the environment background to be linearly combined. Aiming at the interference of interframe random sampling noise, virtual motion is added into the observation vectors and the noise is filtered after the process of image reconstruction. Finally, an environment vector is separated from a motion vector by a matrix partitioning method to realize the test of the motion object and finally mark a tested object region into the image in a way of externally connected rectangle frame. The invention simultaneously discloses a device for testing motion. The invention can be applicable for the monitoring environment of complex colors; design implementation thereof uses the way of period processing to execute the real-time monitoring of the motion and self-adaptively locates the object region; and the invention is a general monitoring visual processing method.

The invention provides a neural network operation device and method. The neural network operation device comprises a submatrix division module, a matrix element storage module, a symbolic operation module, a numerical value operation module, an accumulation module and a convolution result acquisition module, wherein the submatrix division module is used for taking a convolution kernel matrix as afirst matrix and taking each submatrix as a second matrix; the matrix element storage module contains multiple storage spaces, and is used for receiving the converted binary number of a matrix element in the first matrix according to a rule; the symbolic operation module is used for determining an operation result sign bit; the numerical value operation module is used for adding matrix elements on corresponding positions, and an addition result moves leftwards for an i-j bit to obtain an operation intermediate result; the accumulation module is used for adding the operation intermediate results in the first storage space to the (i-1)th storage space to obtain the multiplication and addition operation results of the first matrix and the second matrix; and the convolution result acquisitionmodule is used for forming a matrix by a plurality of multiplication and addition operation results as a convolution operation result according to a sliding sequence.

The invention relates to a matrix partitioning-based realizing method of a high-speed LDPC encoder, which pertains to the technical field of channel coding. The method of the invention comprises the following specific steps that: (1) an LDPC code provided with a partitioning check matrix is constructed; firstly, a check matrix is constructed by using an algebraic approach; the check matrix has no circlet so as to guarantee the performance of the constructed code word; and then the rows of the check matrix are rearranged according to a certain rule to lead the rearranged check matrix to have the partition structure; (2) under a state that the check matrix of the LDPC code has the partition structure, the high-speed parallel decoding of the LDPC code is realized. The realizing method of the invention can realize the high-speed parallel decoding of the LDPC code in engineering; the complexity of the decoding is very low and the constructed code word has no circlet but good performance which is comparable to that of the code word which is constructed randomly.

The invention provides an efficient robust self-adapting beam forming method of broadband. The method is applied to the field of wireless communication and comprises steps as follows: performing fast fourier transform (FFT) to received data of an array to obtain the received data on different frequency points and a covariance matrix of the received data of each frequency point; choosing a central frequency point as a reference frequency point; using a propagator thought to respectively performing matrix partitioning on the covariance matrix of each frequency point and the covariance matrix of the central frequency point so as to obtain a propagator of each frequency point and the propagator of the central frequency point; constructing a focusing transformation matrix, focusing the propagators of different frequency points onto the same reference frequency point to obtain the final propagator estimation and noise subspace; and combining with a feature space method to configure a broadband beam forming algorithm weight vector to realize robust self-adapting beam forming of the broadband. In comparison with a traditional coherent signal subspace method, the method does not need any singular value or feature value decomposition, does not need a diagonal loading technique, and can reflect a good performance with respect to an environment having low snapshots and strong desired signals. Particularly, the method has stronger robustness and reduces the complexity under a condition that the desired signal estimation has a certain error.

The invention provides a method and a device for solving a triangular linear equation set of a multiprocessor system. The multiprocessor system comprises at least one core processor and a plurality ofaccelerators. The method comprises the following steps: dividing matrixes which need to solve the triangular linear equation set into a plurality of sub-matrixes according to the sizes of the scheduled sub-matrixes; calculating and updating the sub-matrixes iteratively; and leading the accelerators to calculate and update the sub-matrixes in parallel, wherein each iteration comprises the following step: distributing the sub-matrixes to the accelerators from the sub-matrixes which are not calculated and updated in the sub-matrixes according to a row direction and the predefined sequence of theaccelerators. The loads of the accelerators can be balanced by distributing matrixes to be solved one by one through the sub-matrixes, and consequently, the calculation ability of the accelerators issufficiently utilized to calculate and update peak value performance.

The invention discloses a mobile terminal comprising an acquisition module, a determination module and a control module, wherein the acquisition module is used for acquiring matrix information that the mobile terminal performs matrix partition on the display screen; the determination module is used for determining whether a finger slides in a preset direction within a preset region on the display screen when a signal that the finger of a user slides on the display screen is monitored; the control module is used for controlling application icons on the display screen within a preset region of the matrix to move correspondingly according to the preset directions successively according to the information of the finger sliding on the display screen and the matrix information when it is determined that the finger slides within the preset region according to the preset direction. The invention also discloses a screen operation control method. By means of the mobile terminal and the screen operation control method thereof, the operability of application icons on the display screen of the mobile terminal is increased in that users can carry out full screen operation of the mobile terminal when the mobile terminal is held with single hand so that user experience is increased.

The invention discloses a multi-sample multi-channel convolutional neural network Same convolution vectorization implementation method, which comprises the steps of 1, storing input feature data set data according to a sample dimension priority mode, and storing data of convolution kernels according to a number dimension priority mode of the convolution kernels; 2, dividing a data matrix of the input feature data set into a plurality of matrix blocks according to columns; step 3, transmitting the convolution kernel data matrix to the SM of each kernel each time, transmitting a sub-matrix formed by row extraction from the input feature data matrix to the AM of each kernel, executing vectorization matrix multiplication calculation and parallelization matrix multiplication calculation, and executing zero supplement in the calculation; 4, storing an output characteristic matrix calculation result in an off-chip memory; and step 5, repeating the steps 3 to 4 until all calculations are completed. According to the invention, Same convolution vectorization can be realized, and the method has the advantages of simple implementation operation, high execution efficiency and precision, small bandwidth requirement and the like.

The invention discloses a partition backlight-based low-delay liquid crystal display device and a driving method thereof. The liquid crystal display device comprises a plurality of partition backlightwhich is distributed in an arrayed manner. The driving method comprises the following steps: S1. performing line-rank scanning to active arrays of a display screen, and acquiring the gray-level of picture of current pixel, to obtain gray-level picture matrix; S2. normalizing the gray-level picture matrix according to the electro-optical curve of the display device, to obtain displayed driving matrix; S3. dividing the displayed driving matrix into displaying partitions correspondingly one by one according to the partition backlight, and acquiring the position of the displaying partition wherethe current pixel is; and S4. Performing the gray-level distribution statistics of each displaying partition according to the position, where the current pixel is, of the displaying partition and thedisplayed driving matrix, calculating the lighting backlight coefficient of each displaying partition according to the gray-level distribution statistics of the displaying partition, and determining the displaying partition needing to be lightened according to the position where the current pixel is in the displaying partition and the position where the current displaying partition is in the displayed driving matrix.

The invention discloses a method for compressing and decompressing acoustic logging data. The compressing method comprises the steps: conducting matrix partitioning on the data collected by an acoustic logging instrument according to the number of collection channels; carrying out discrete cosine transform on each block matrix to obtain a DCT coefficient matrix; designing an appropriate quantization matrix according to the characteristics of the sound wave signals, and quantizing the DCT coefficient matrix; carrying out run-length coding and Huffman coding on the quantized matrix; and obtaining a compressed code stream and transmitting the compressed code stream. According to the compressing method, on the basis that the calculation performance of a downhole main control device is improved, a high compression ratio is achieved. According to the method, the data can be compressed in real time downhole, and the data transmission amount is greatly reduced, so that the logging speed of the acoustic logging instrument is increased.

The invention discloses a DDR-based high-efficiency matrix transposition processing method. The method comprises the following steps of matching a write RAM and a read RAM with an IP core of a DDR3 SDRAM; wherein a to-be-transposed matrix is a 128 * 128 matrix with 64 bits of single data, and data of each row of the to-be-transposed matrix is taken as a small matrix; writing 16 data in each activesignal in the writing operation process; reading 8 * 16 pieces of data by each active signal in the reading operation process; and performing reading in DDR according to a same inter-row and data cyclic skip rule, so that the occurrence of row active signals is reduced as much as possible. According to the invention, the problem that the overall processing rate of the system is reduced due to the jump access of the DDR SDRAM in large-order matrix transposition is solved. By the matrix partitioning technology, on the basis that the writing rate is reduced to a small extent, the reading rate is greatly increased, the DDR reading and writing rate is balanced when a matrix is transposed, and therefore the average DDR reading and writing efficiency is improved.

A method for extracting an illuminated zone from a matrix of photosensors may include: (a) dividing the matrix into a plurality of search zones, (b) searching for the presence of an active photosensor in the search zones, (c) stopping the search as soon as an active photosensor is found in a search zone, and (d) further subdividing the first search zone determined to have an active photosensor into a plurality of search zones. Additionally the method may include repeating steps (b) through (d) until a search zone having only active photosensors is obtained.

A graphic character that has a character matrix with a number of character units that are indivisible at least in either a horizontal direction or a vertical direction is scaled by dividing the character matrix into one first and at least one second character segment, each comprising at least one of the character units. The first character segment is symmetrically scaled using a first scaling factor and the second character segment is scaled using a second scaling factor different from the first scaling factor.

The invention discloses a data processing method based on a deep neural network. The method comprises the steps of obtaining an input matrix input to a hidden layer of the deep neural network; Judgingwhether the operation type of the hidden layer is a matrix multiplication operation or not; If yes, respectively partitioning the input matrix and the network parameter matrix of the hidden layer according to a preset matrix partitioning rule, and respectively distributing the partitioned input matrix and the partitioned network parameter matrix to a plurality of computing nodes to carry out matrix multiplication operation; Obtaining a partitioning calculation result, and combining the partitioning calculation result to obtain an output matrix of the hidden layer; Outputting the output matrix. The invention also discloses a data processing system of the deep neural network, a terminal and a medium. According to the method, the operation speed of matrix multiplication operation in the deepneural network can be improved, so that the overall calculation time is shortened.

The invention discloses a matrix operation method and device, a storage medium and a terminal. The matrix operation method comprises the steps of obtaining at least one matrix; formatting each matrixin the at least one matrix to obtain each formatted matrix, the formatting comprising: dividing the matrix into a plurality of sub-matrixes, transposing each sub-matrix, and marking each transposed sub-matrix as a tile; and in response to a matrix operation instruction, performing operation on each formatted matrix to obtain an operation result. Through the scheme provided by the invention, matrixoperation can be carried out based on a more efficient data format, and especially in a multi-process scene, the data operation amount can be greatly reduced, and the transmission bandwidth requirement from a computer to a memory is optimized, and the execution delay in the operation period is reduced.

The invention discloses a convolution operation optimization method and system for efficiently running a deep learning task. The method comprises the following steps: obtaining picture parameters andconvolution kernel parameters, segmenting the picture parameters and the convolution kernel parameters to obtain picture sub-tensors and convolution kernel sub-tensors, copying the segmented sub-tensors to a high-speed memory, performing convolution operation on the sub-tensors stored in an L1 cache, and assembling the sub-tensors subjected to convolution operation according to an assembling stepof a matrix partitioning algorithm to obtain a final result. Through matrixes and tensor partitioning strategies adjusted according to hardware parameters of different embedded platforms, in the wholeoperation process, more operation data can be obtained from a high-speed memory instead of low-speed storage, and the operation speed is increased; meanwhile, through a reasonable strategy for optimizing the assembly level of the embedded platform, the potential of the platform can be better utilized by operation, and the operation speed is further increased; in addition, a matrix partitioning strategy is adopted, so that the implementation cost is lower.