High speed LDPC decoder implementing method based on matrix block

A technology of LDPC codes and implementation methods, which is applied in the field of channel coding, and can solve problems such as ineffective work, impractical medium-speed systems, and slow reading and writing speeds.

Inactive Publication Date: 2008-12-31
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

At this time, although multiple CNU units and VNU units can work at the same time, since L(q ij ) or L(r ji ) The speed of reading and writing numbers is slow, most of the time it is in a waiting state, cannot work effectively, and parallel operations cannot be realized
[0027] One solution is to put L(q ij ) and L(r ji Each data in ) is stored in a

Method used

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  • High speed LDPC decoder implementing method based on matrix block
  • High speed LDPC decoder implementing method based on matrix block
  • High speed LDPC decoder implementing method based on matrix block

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Embodiment Construction

[0086] The present invention will be further described below in conjunction with accompanying drawing and an example.

[0087] The implementation and construction of a high-speed LDPC decoder based on matrix block mainly includes two parts: constructing an LDPC code with block structure check matrix, and the constructed codeword has no small rings, thus ensuring the performance of the constructed codeword; For codewords with block check matrix, according to the BP algorithm, the LDPC decoder is realized by using a partially parallel decoding structure or a fully parallel decoding structure.

[0088] Suppose the code word to be designed is (1008, 504), the code rate is 1 / 2, the column weight is q=3, and the row weight is the regular LDPC code of p=6, that is, the information bit length of the code word is 504, and after encoding If the code length is 1008, then the parity bit length is M=1008-504=504. Then the process of constructing a check matrix codeword with block structur...

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Abstract

The invention relates to a matrix partitioning-based realizing method of a high-speed LDPC encoder, which pertains to the technical field of channel coding. The method of the invention comprises the following specific steps that: (1) an LDPC code provided with a partitioning check matrix is constructed; firstly, a check matrix is constructed by using an algebraic approach; the check matrix has no circlet so as to guarantee the performance of the constructed code word; and then the rows of the check matrix are rearranged according to a certain rule to lead the rearranged check matrix to have the partition structure; (2) under a state that the check matrix of the LDPC code has the partition structure, the high-speed parallel decoding of the LDPC code is realized. The realizing method of the invention can realize the high-speed parallel decoding of the LDPC code in engineering; the complexity of the decoding is very low and the constructed code word has no circlet but good performance which is comparable to that of the code word which is constructed randomly.

Description

technical field [0001] The invention relates to an LDPC decoding method, in particular to a method for realizing a high-speed LDPC decoder based on matrix partitioning, and belongs to the technical field of channel coding. Background technique [0002] In satellite communication, deep space communication and various wireless communication systems, in order to improve the anti-noise ability of the system, channel coding is essential. Among all current channel codes, LDPC codes are the closest good codes to the Shannon limit, and their performance is better than Turbo codes. The decoding of LDPC codes adopts BP (Belief Propagation) iterative decoding algorithm, which not only has good decoding performance, but also has linear decoding complexity. More importantly, this is a parallel decoding algorithm, which can be extremely Greatly improve decoding speed. However, in engineering implementation, for completely randomly constructed codewords, the reading and writing speed of ...

Claims

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Application Information

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IPC IPC(8): H04L1/00H03M13/00
Inventor 安建平刘策伦卜祥元王忠勇
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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