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151 results about "Identity matrix" patented technology

In linear algebra, the identity matrix, or sometimes ambiguously called a unit matrix, of size n is the n × n square matrix with ones on the main diagonal and zeros elsewhere. It is denoted by Iₙ, or simply by I if the size is immaterial or can be trivially determined by the context. (In some fields, such as quantum mechanics, the identity matrix is denoted by a boldface one, 1; otherwise it is identical to I.) Less frequently, some mathematics books use U or E to represent the identity matrix, meaning "unit matrix" and the German word Einheitsmatrix respectively.

Hardware-efficient low density parity check code for digital communications

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes. Variations including parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.
Owner:TEXAS INSTR INC

Hardware-Efficient Low Density Parity Check Code for Digital Communications

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclosed. The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes. Variations including parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.
Owner:TEXAS INSTR INC

Low-complexity quick parallel matrix inversion method

The invention discloses a low-complexity quick parallel matrix inversion method. The method comprises the following steps that first, a matrix A is given, a matrix E is made to be a unit matrix with the same order as the matrix A, the matrix A and the matrix E form an expanding matrix B, modified Givens rotation (MSGR, Modified Square Givens Rotations) is carried out on the matrix B, an upper triangular matrix U and , wherein according to the define of the matrix U and , an SGR (Squared Givens Rotations) method is used for deforming the QR division of the matrix A according to the equation, and the relation between the QR division and original QR division meets the equations , , , and ; according to the MSRG method, the square root operation in the process of Givens rotation can be omitted while division operation is reduced, and algorithm complexity is obviously reduced; second, a back substitution method is used for working out the inverse matrix U-1 of the upper triangular matrix U; third, matrix inversion is carried out according to the equation . According to the low-complexity quick parallel matrix inversion method, a large amount of division operation and a large amount of square root operation are omitted, algorithm complexity is reduced, and the method can be used for matrix inversion of the fields of wireless communication, signal processing and numerical calculation.
Owner:南京易太可通信技术有限公司
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