154results about How to "Suppression frequency" patented technology

A wireless power enabled apparatus includes a wireless power receiver. The wireless power receiver includes a receive coil, a rectifier, a regulator, and a damping circuit. The receive coil is configured to generate an AC power signal responsive to a wireless power signal. The rectifier is configured to receive the AC power signal and generate a DC rectified power signal relative to a rectified ground signal. The regulator is operably coupled with the rectifier to receive the DC rectified power signal and generate an output voltage. The damping circuit is operably coupled between the DC rectified power signal and the rectified ground signal and in parallel with the regulator. The damping circuit is configured to suppress audible harmonics generated by the wireless power receiver at some loads by providing a damping impedance for the DC rectified power signal.

Disclosed is a multi-wavelength locking method for a wavelength division multiplexing (WDM) optical communication network, and in particular, a multi-wavelength locking method and apparatus for a WDM optical communication system that can lock wavelengths of optical signals by producing pilot tones by applying a sine-wave current to a plurality of transmission lasers having different wavelengths, passing the optical signal through a Fabry-Perot etalon filter, and then Fourier-transforming the filtered optical signal. The multi-wavelength locking method includes frequency-modulating an optical signal by applying a small and specified sine-wave current to a bias current for driving WDM lasers, detecting pilot tones produced after filtering the optical signal through a filtering section and converting the detected signal into a digital signal by performing a sampling of the detected signal, detecting a magnitude and phase of the pilot tones by performing a fast Fourier transform, providing Fourier-transformed data as a first derivative signal of the filtering section, and locking an operation wavelength of WDM channels by controlling the temperature or current if resonance frequencies of the filtering section coincide with respective standard frequency.

A piezoelectric device includes a base substrate constituting the bottom of the package; a framed resonator element layered on the base substrate; and a lid for hermetically sealing a space within the package, the lid being layered on the framed resonator element. The framed resonator element includes a frame constituting a wall surrounding the space within the package; a base having a predetermined width, which is integrally formed inside the frame; a plurality of resonating arms that extend in parallel to each other from the base in one direction in the frame; first cutouts that are provided near the base ends of the resonating arms in the base; and second cutouts formed at the joint between the base and the frame.

The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

A cache server control device selects cache servers necessary for storing contents to be reproduced, and allows the selected cache servers 300 store the contents to be reproduced; the cache server control device herein uses a first threshold value when the number of units of the cache servers, for storing the content to be reproduced related to the judgment, is increased; and uses a second threshold value, being smaller than the first threshold value, when the number of units of the cache servers, for storing said content to be reproduced related to the judgment, is decreased.

The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

Provided is a method for controlling an information processing system including a relay service device, an intermediate service device, and an authentication service device. The control method includes transmitting an authentication request from the intermediate service device to the intermediate service device; acquiring a first access token from the authentication service device that has made a success of authentication; storing the first access token; comparing the stored first access token with a second access token included in an execution request of an relation processing upon reception of the processing execution request from the relay service; and executing processing received from the intermediate service device when it is determined in the comparing that the first access token matches the second access token or not executing the processing when it is determined in the comparing that the first access token does not match the second access token.

A semiconductor display device which can suppress the drive frequency while increasing the number of gray scales. According to the semiconductor display device, a plurality of pixels can be selected per row by a first scan line driver circuit, the plurality of pixels can be selected per row by a second scan line driver circuit, writing of a first video signal to the row selected by the first scan line driver circuit is controlled by a signal line driver circuit, writing of a second video signal to the row selected by the second scan line driver circuit is controlled by the signal line driver circuit, and using respective selection circuits included in the first and second scan line driver circuits, the output from the second scan line driver circuit to the plurality of pixels can be set at high impedance while the row is selected by the first scan line driver circuit, or the output from the first scan line driver circuit to the plurality of pixels can be set at high impedance while the row is selected by the second scan line driver circuit.

Disclosed is a current-mode control switching regulator that steps down or steps up an input voltage input to an input terminal to a predetermined constant voltage and outputs the stepped input voltage from an output terminal as an output voltage. The current-mode control switching regulator includes a switching element, an inductor, a rectifying element, an error amplification circuit unit, an oscillation circuit unit with variable oscillation frequency, a slope voltage generation circuit unit, and a switching control circuit unit.

The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. By using a transformation check matrix obtained by performing one of or both a row permutation and a column permutation on an original check matrix of LDPC (Low Density Parity Check) codes, the LDPC codes are decoded. In this case, by using, as a formation matrix, a P×P unit matrix, a quasi-unit matrix in which one or more is, which are elements of the unit matrix, are substituted with 0, a shift matrix in which the unit matrix or the quasi-unit matrix is cyclically shifted, a sum matrix, which is the sum of two or more of the unit matrix, the quasi-unit matrix, and the shift matrix, and a P×P 0-matrix, the transformation check matrix is represented by a combination of a plurality of the formation matrices. A check node calculator 302 simultaneously performs p check node calculations. A variable node calculator 304 simultaneously performs p variable node calculations.

A linear regulator circuit for suppressing power supply noise that propagates to an output voltage. An LDO circuit functioning as the linear regulator circuit is provided with an output transistor including a source for receiving input voltage, a drain for outputting the output voltage, and a control terminal. An error amplifier powered by the input voltage generates a control voltage for controlling the output transistor based on a potential difference between a feedback voltage, which corresponds to the output voltage, and a reference voltage. A first capacitor and a resistor are connected in series between the source of the output transistor and an output terminal of the error amplifier.

In an ignition timing control apparatus for an engine, a KCS learning value learned when the engine is in a given operating state is used in an ignition timing control executed when the engine is in the other operating state. An estimated knocking occurrence ignition timing is set based on a most retarded ignition timing using the KCS learning value. A final ignition timing is set by changing a KCS feedback correction value based on whether knocking occurs when ignition is performed at the estimated knocking occurrence ignition timing. When a point indicating the engine operating state moves into a region where it is difficult to set the estimated knocking occurrence ignition timing, the KCS feedback correction value is changed to retard the final ignition timing, and the final ignition timing is set using the KCS learning value and the changed KCS feedback correction value.

The invention discloses a method for designing an LCL (Logical Connection Layer) filter by uniformly controlling photovoltaic grid connection and active power filtering. The method comprises the following steps of: (1) determining the total inductance value LT of the LCL filter; (2) determining the filtering capacitance value Cf of the LCL filter; and (3) determining the resonance frequency fres of the LCL filter. According to the method, the LCL filter is designed on the basis of uniform control over a photovoltaic grid-connected system and active power filtering by using power grid accessing current which is provided with fundamental waves and resonant waves under the comprehensive consideration of the restraint conditions of the control applications of the fundamental waves and the resonant waves; and as proved by verification, the LCL filter can be used for effectively restraining switching frequency and higher-order harmonics, a satisfied photovoltaic grid connection effect can be achieved in combination with modeling control, and idle work required by a power grid is compensated properly.

A piezoelectric substrate includes rod-shaped resonating arms; a base portion that connects one set of end portions of the respective resonating arms; weight portions which are formed on the other end portions of the respective resonating arms and which have a width larger than that of the respective resonating arms; and groove portions which are formed on each of the front and rear surfaces along the center line of vibration of the respective resonating arms. The piezoelectric substrate also includes excitation electrodes which are formed on each of the front and rear surfaces of the respective resonating arms including the inner side of the respective groove portions. A plurality of frequency adjustment slits extending in a straight line form along the longitudinal direction of the respective resonating arms are formed on the respective weight portions so as to penetrate through the front and rear surfaces of the weight portions.

The invention discloses an independent micro-grid layered coordinated control method based on different time scales. The method comprises the following steps of (1), according to the dynamic characteristics of voltage and frequency of an independent micro-grid system, dividing the fluctuation range of the voltage and frequency into three areas of A, B and C, wherein the area A represents that the deviation of the voltage and frequency is in a normal fluctuation range, the area B represents that the deviation of the voltage and frequency slightly exceeds the normal fluctuation range, and the area C represents that the deviation of the voltage and frequency seriously exceeds the normal fluctuation range; (2) monitoring and collecting the voltage U, the frequency f and the power P of the bus of the independent micro-grid, and determining the areas where the U and the f are located; (3) if the U and the f are located in the area A, keeping a storage battery energy storage system and a diesel generating set away from an adjustment process, if the U and the f are located in the area B, enabling the storage battery energy storage system in charge of primary control to participate in the adjustment process to achieve system power balance, and if the U and the f are located in the area C, enabling a secondary control diesel generator to participate in the adjustment process to achieve system power balance; (4) repeatedly collecting the U, the f and the P until the U and the f are determined to be located in the area A.

A semiconductor display device with which flicker, vertical striping, and horizontal striping are not easily seen, and a method of driving the semiconductor display device, are provided. Display signals inputted to a plurality of pixel electrodes have a positive or negative polarity based on the electric potential of an opposing electrode, and pixel electrodes to which display signals having a positive polarity are inputted, and pixel electrodes to which display signals having a negative polarity are inputted, differ for each frame period with the method of driving the semiconductor display device.

Highly efficient gene transfer into primate-derived embryonic stem (ES) cells has successfully been achieved by using a simian immunodeficiency virus vector (SIV) pseudotyped with VSV-G protein, which is a surface glycoprotein of vesicular stomatitis virus (VSV) The present invention provides simian immunodeficiency virus vectors for gene transfer to primate ES cells. The method for gene transfer to primate ES cells using the vectors of the present invention is useful in, for example, research into embryology and disease, clinical applications, and experimental models for primates. The method is also useful in assaying and screening for genes and reagents able to enhance the specific differentiation of tissues or cells, and which are useful in preparing desired cells or tissues differentiated from ES cells.

A piezoelectric device includes a base substrate constituting the bottom of the package; a framed resonator element layered on the base substrate; and a lid for hermetically sealing a space within the package, the lid being layered on the framed resonator element. The framed resonator element includes a frame constituting a wall surrounding the space within the package; a base having a predetermined width, which is integrally formed inside the frame; a plurality of resonating arms that extend in parallel to each other from the base in one direction in the frame; first cutouts that are provided near the base ends of the resonating arms in the base; and second cutouts formed at the joint between the base and the frame.

The invention discloses a method for carrying out real-time error compensation on an atomic clock to reduce frequency deviation. Through monitoring an environmental noise variable, an error signal which is affected by the environmental noise variable is compensated and is fed back to a local oscillator in real time to inhibit the effect of the environmental noise, the limitations to atoms and environmental fluctuation control thereof are broken, the frequency uncertainty of the atomic clock is remarkably reduced, and meanwhile, the stability of the atomic clock is improved.

The invention discloses a TPS time synchronization improving algorithm based on an IEEE1588 synchronization mechanism, and belongs to the technical field of accurate clock synchronization. The TPS time synchronization improving algorithm based the IEEE1588 synchronization mechanism includes following steps: step 1, statistically calculating clock frequency deviation, and completing frequency synchronization; step 2, statistically calculating synchronous time deviation, communication time delay and the minimum number of messages needed for achieving designated accurate time synchronization, and completing initial time synchronization based on symmetry time delay; step 3, completing the accurate time synchronization based on the symmetry time delay by using the minimum message number, building fuzzy control which uses transmission error and transmission error change rate as input in the subsequent process, and performing on-line time deviation and frequency change adjustment. The TPS time synchronization improving algorithm based the IEEE1588 synchronization mechanism is compatible with the IEEE1588 synchronization mechanism well, provides the time synchronization more accurate than time synchronization provided by the IEEE1588 synchronization mechanism, effectively restrains a frequency drift problem and a random fluctuation problem in the time synchronization, can adapt to abrupt change of network topology, and can save a large amount of synchronization message spending in long time running.

An information display device includes: an automatic driving control unit configured to perform automatic driving, the automatic driving including at least road-tracking automatic driving in which a vehicle travels automatically while maintaining a traveling lane or a traveling road without setting a destination; and a display control unit configured to display at least one of a distance and a traveling time from a position of the vehicle to a branch point of the traveling road in which the vehicle travels or a point at which the road-tracking automatic driving ends on a display unit when the road-tracking automatic driving is performed by the automatic driving control unit.

The present invention provides a hairspring supporting structure which can adjust the offset of the hairspring from a plane to a lowest limit, a hairspring balance wheel structure and a mechanical clock. The hairspring supporting structure of mechanical clock comprises a hairspring stud height position adjusting mechanism which shifts the hairspring stud in a vertical direction relatively to a hairspring stud ring. The hairspring stud is provided with a shaft which is inserted and penetrates the hairspring stud ring and a disc-shaped flange. The hairspring stud height position adjusting mechanism is provided with a hairspring stud height position adjustor which comprises the following components: an adjusting shaft which is matched with the hairspring stud ring; and an adjustor body which is provided with a reference frustum-shaped surface which is eccentric relatively the adjusting shaft at one side of the adjusting shaft. When the hairspring stud height position adjustor rotates along a central axis of the adjusting shaft, the adjustor body presses one end edge of the disc-shaped flange of the hairspring stud thereby shifting the hairspring stud upwards or downwards relatively to the hairspring stud ring.

An engine start control apparatus for a vehicle in which an engine can be automatically stopped temporarily is characterized in that when the position of a piston is within a range that is likely to cause ignition during automatic stop of the engine (Yes in step S3), it is predicted that the electric power consumed in a starting device in restarting the engine is small, a second path with a large resistance is selected as an energization path from a battery to a starter motor (step S4), and starter start for cranking the engine by the starting device and ignition start based on fuel injection and ignition are executed (step S5) to restart the engine.

A bulk acoustic wave (BAW) filter (40) is fabricated from thin film bulk acoustic wave resonators and a method eliminates unwanted side passbands. This BAW filter comprises a substrate (14) a resonator section (11) and an acoustic mirror section (12). Further it comprises a detuning component (31) positioned in the resonator section (11) to provide precise passband characteristics and an additional detuning component (41) in the acoustic mirror section (12) to suppress unwanted side-passband characteristics.

A space vector pulse width modulation (SVPWM) method for suppressing a common-mode voltage of a multiphase motor includes the following steps: (1) dividing all basic vectors of the multiphase motor into q types, and selecting therefrom x types having equal common-mode voltage magnitude of which an absolute value is smallest; (2) for each type in the x types of basic vectors, structuring y classes of auxiliary vectors according to an optimization model; (3) synthesizing reference vectors by virtue of the auxiliary vectors to obtain functioning time of basic vectors functioning in each switching period; and (4) obtaining an optimal functioning sequence of the basic vectors functioning in each switching period with fewest switching operations of a converter as a purpose. The present invention may effectively suppress a magnitude and frequency of the common-mode voltage of the multiphase motor without increasing calculation complexity or reducing other performance indexes, has a good harmonic suppression effect on a line voltage and a phase current and high steady state and dynamic performance of a torque and a rotating speed, and can be used for a high-performance multiphase power generation system, a multiphase excitation system and a multiphase driving system.

In an ignition timing control apparatus for an engine, a KCS learning value learned when the engine is in a given operating state is used in an ignition timing control executed when the engine is in the other operating state. An estimated knocking occurrence ignition timing is set based on a most retarded ignition timing using the KCS learning value. A final ignition timing is set by changing a KCS feedback correction value based on whether knocking occurs when ignition is performed at the estimated knocking occurrence ignition timing. When a point indicating the engine operating state moves into a region where it is difficult to set the estimated knocking occurrence ignition timing, the KCS feedback correction value is changed to retard the final ignition timing, and the final ignition timing is set using the KCS learning value and the changed KCS feedback correction value.

In a vehicle drive control apparatus, a behavior determination unit determines whether a vehicle behavior is in a stable state or an unstable state based on a vehicle turning behavior. An engine stop control unit avoids stopping the engine as automatic stop conditions are not satisfied when the vehicle behavior is determined to be in an unstable state during operation of the engine. When the vehicle behavior is in a stable state and other automatic stop conditions are satisfied during operation of the engine, the engine stop control unit stops the engine. During stability control performed by a stability ECU, the engine stop control unit avoids stopping the engine as the automatic stop conditions are not satisfied.