228results about How to "Suppression voltage" patented technology

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

A plasma processing method and apparatus are provided for processing the surface of a semiconductor device or the like through the effect of plasma. A pulsed plasma discharge is performed by switching on and off the high frequency electric power for generating the plasma with a specified off period of the plasma generation, to control an inflow amount of positive and negative charges to sparse and dense portions of device patterns and suppress an electric potential on a gate oxide film. Thereby, a highly accurate etching process with no charging damage can be carried out.

In an electric power storage system according to the present invention, in the case of charging, a plurality of capacitors of each circuit block of the electric power storage system are switched to a serial connection to initiate the charging. When the output voltage of power storage means reaches the maximum input voltage of DC-AC conversion means, each capacitor of a number j of circuit blocks is switched to a parallel connection in order of higher block voltage. Also up to the time when the maximum input voltage is reached again, each capacitor of a number j of circuit blocks is switched to a parallel connection in order of higher block voltage. In the case of discharging, pluralities of capacitors of each circuit block of the electric power storage system are switched to a parallel connection to initiate the discharging. When the output voltage of power storage means reaches the minimum input voltage of DC-AC conversion means, each capacitor of a number k of circuit blocks is switched to a serial connection in order of higher block voltage. Also up to the time when the minimum input voltage is reached gain, each capacitor of a number k of circuit blocks is switched to a serial connection in order of higher block voltage. Accordingly, the electric power storage system is hardly affected by the capacitance error of the capacitors, and charging / discharging efficiency can be improved.

A transparent-substrate light-emitting diode (10) has a light-emitting layer (133) made of a compound semiconductor, wherein the area (A) of a light-extracting surface having formed thereon a first electrode (15) and a second electrode (16) differing in polarity from the first electrode (15), the area (B) of a light-emitting layer (133) formed as approximating to the light-extracting surface and the area (C) of the back surface of a light-emitting diode falling on the side opposite the side for forming the first electrode (15) and the second electrode (16) are so related as to satisfy the relation of A>C>B. The light-emitting diode (10) of this invention, owing to the relation of the area of the light-emitting layer (133) and the area of the back surface (23) of the transparent substrate and the optimization of the shape of a side face of the transparent substrate (14), exhibits high brightness and high exoergic property never attained heretofore and fits use with an electric current of high degree.

A plasma processing method and apparatus are provided for processing the surface of a semiconductor device or the like through the effect of plasma. A pulsed plasma discharge is performed by switching on and off the high frequency electric power for generating the plasma with a specified off period of the plasma generation, to control an inflow amount of positive and negative charges to sparse and dense portions of device patterns and suppress an electric potential on a gate oxide film. Thereby, a highly accurate etching process with no charging damage can be carried out.

A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

A piezoelectric film formed above a Si substrate. The piezoelectric film is formed of a potassium sodium niobate expressed by a general formula (K,Na)NbO3 with perovskite structure. A film thickness of the piezoelectric film is within a range from 0.3 μm to 10 μm. An intermediate film is formed between the Si substrate and the piezoelectric film. The intermediate film generates a stress in a compressive direction in the piezoelectric film.

Provided are a battery pack manufacturing method, which can prevent a drawback that some of used secondary batteries constituting a battery pack prematurely come to the end and which can suppress the enlargement of the temporary voltage difference between the used secondary battery at a charging / discharging time (especially in a low-temperature circumstance), and a battery pack. The battery pack manufacturing method comprises an acquiring step (Step S1) of acquiring the individual internal resistances of the secondary batteries already used, a selection step (Step S2) of selecting a plurality of the used secondary batteries having the internal resistances close to each other from a group of the used secondary batteries whose internal resistances have been acquired, and an assembling step (Step S3) of combining the used secondary batteries selected, to constitute the battery pack.

A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating film inserted between the gate, and the source and drain. A plurality of signal lines are patterned together with the gates of the driving transistors and arrayed to run in a predetermined direction on the substrate. A plurality of supply lines are patterned together with the sources and drains of the driving transistors and arrayed to cross the signal lines via the gate insulating film. The supply line is electrically connected to one of the source and the drain of the driving transistor. A plurality of feed interconnections are formed on the supply lines along the supply lines, respectively.

A ripple voltage suppression apparatus includes a DC / DC converter and a control circuit. The DC / DC converter has a power electronic switch. The control circuit has a voltage detector detecting a DC output voltage of the DC / DC converter, a ripple voltage suppression circuit receiving the detected DC output voltage to generate an AC control signal for controlling an AC component of a duty ratio of the power electronic switch, an output voltage regulation circuit receiving the detected DC output voltage to generate a DC control signal for controlling an DC component of a duty ratio, an adder adding the AC and DC control signals to form a combined control signal, and a PWM circuit converting the combined control signal into a PWM signal to control the power electronic switch. Only the DC output voltage of the DC / DC converter has to be detected for the control circuit.

The invention is made in view of solving problems in reduction in yield and an aperture ratio in accordance with an increase in the number of transistors which form a pixel, increase in power consumption for holding predetermined luminance to provide a light emitting device having a noble pixel configuration. A light emitting device of the invention includes a unit for applying a forward bias voltage to a first light emitting element so that a first pixel emits light and applying a reverse bias voltage to a second light emitting element, and a unit for applying a reverse bias voltage to the first light emitting element so that the first pixel emits no light and applying a forward bias voltage to the second light emitting element.

On a termination side of each scanning line is provided a charging switching element and a discharging switching element in parallel with each other, the charging switching element having a gate electrode which is connected with one end of a scanning auxiliary line, the other end of which is connected to a scanning line of the same stage, the discharging switching element having a gate electrode which is connected with one end of a scanning auxiliary line, the other end of which is connected to a scanning line of the following stage. Further, the charging switching element has a source / drain electrode which is connected to a scanning line and a selected state scanning driving voltage power source, whereas the discharging switching element has a source / drain electrode which is connected to a scanning line and the non-selected state scanning driving voltage power source, thereby allowing an image display device of the present invention to suppress the dull waveform of a driving voltage at both rise and fall, and prevent erroneous writing without reducing effective writing time.

A first inverter control unit includes a harmonic generation unit. The harmonic generation unit generates a harmonic voltage instruction having a phase opposite to a harmonic generated at a neutral point of a motor-generator when the motor-generator revolves, based on motor revolution number of the motor-generator. A PWM signal generation unit generates a signal based on a voltage instruction obtained by superimposing an AC voltage instruction from an AC output control unit and the harmonic voltage instruction from the harmonic generation unit onto each voltage instruction of U-phase, V-phase and W-phase from a conversion unit.

In a protection circuit for protecting semiconductor integrated circuit devices from an electrostatic breakdown or a latch-up due to an external surge, etc, a drain terminal of a PMOS transistor MP1, having a source terminal connected to a power supply VDD and a gate terminal receiving a control signal VG1 which a control circuit 2 generates on the basis of a power supply GND, is connected to one end of a resistor R1, having the other end connected to the power supply GND, and to a gate terminal of an NMOS transistor MN1 having a drain terminal and a source terminal connected to the power supply VDD and the power supply GND, respectively, and outputs an internal signal VG2 to the gate terminal of the NMOS transistor. When a predetermined voltage or more is applied to the power supply, the power supply is short-circuited.

A power conversion apparatus has a rectification circuit provided for converting AC power supplied from an AC power supply into DC power. The rectification circuit has a configuration in which series circuit whose number corresponds to the number of phases of an input AC are connected in parallel between a positive-side line and a negative-side line. The AC power supply is connected to AC input points, each corresponding to a connection point between a rectifying device and a semiconductor switching device in each of the series circuits, and connected to a point having ground potential through noise suppressing series circuits respectively. In each of the noise suppressing series circuits, a switch unit and a capacitor are connected in series. In this manner, it is possible to provide a power conversion apparatus which can reduce a noise terminal voltage while solving problems in volume and cost simultaneously.

An AC command voltage obtained by compensating a reference value of a commercial AC voltage output from a multiplication unit using an FB control unit is multiplied by k (0≦k≦1) by a multiplication unit and output to a first inverter control unit, and the remaining part is output to a second inverter control unit. The first and second inverter control units generate signals, based on command voltages obtained by superposing the AC command voltage from an AC output control unit on respective phase command voltages.

A q-axis target current setting unit generates a q-axis current command value based on a steering input signal from a steering torque sensor and a vehicle speed signal from a vehicle speed sensor. An electric motor generates a predetermined torque based on the q-axis current command value and a q-axis current (a torque current) to which a fed back q-axis real current is added. On the other hand, a d-axis correction current setting unit sets a field weakening current (a d-axis current) in response to a voltage saturation (duty ratio=driving voltage of electric motor / power supply voltage) output from a voltage saturation calculating unit. For this reason, when the voltage saturation becomes high, distortion (harmonics component) in current can be decreased by decreasing the voltage saturation while keeping the torque constant using a predetermined torque current, and a torque ripple can be suppressed.

In an electric power storage system according to the present invention, in the case of charging, a plurality of capacitors of each circuit block of the electric power storage system are switched to a serial connection to initiate the charging. When the output voltage of power storage means reaches the maximum input voltage of DC-AC conversion means, each capacitor of a number j of circuit blocks is switched to a parallel connection in order of higher block voltage. Also up to the time when the maximum input voltage is reached again, each capacitor of a number j of circuit blocks is switched to a parallel connection in order of higher block voltage. In the case of discharging, pluralities of capacitors of each circuit block of the electric power storage system are switched to a parallel connection to initiate the discharging. When the output voltage of power storage means reaches the minimum input voltage of DC-AC conversion means, each capacitor of a number k of circuit blocks is switched to a serial connection in order of higher block voltage. Also up to the time when the minimum input voltage is reached gain, each capacitor of a number k of circuit blocks is switched to a serial connection in order of higher block voltage. Accordingly, the electric power storage system is hardly affected by the capacitance error of the capacitors, and charging / discharging efficiency can be improved.

The invention is made in view of solving problems in reduction in yield and an aperture ratio in accordance with an increase in the number of transistors which form a pixel, increase in power consumption for holding predetermined luminance to provide a light emitting device having a noble pixel configuration. A light emitting device of the invention includes a unit for applying a forward bias voltage to a first light emitting element so that a first pixel emits light and applying a reverse bias voltage to a second light emitting element, and a unit for applying a reverse bias voltage to the first light emitting element so that the first pixel emits no light and applying a forward bias voltage to the second light emitting element.

A driving apparatus including an inverter unit for energizing the coil by switching ON and OFF of the switching element, an energization pattern determination unit for selecting a plurality of energization patterns, each of which indicates a direction of a current that flows through the coil, one by one when driving of a motor is started, and energizing the coil by switching ON and OFF of the switching element based on a selected energization pattern at a duty ratio corresponding to a value of a maximum current capable of being supplied by the power supply apparatus, a current applied time measurement unit for measuring an energization time, which is a time until a value of the current flowing through the coil reaches a predetermined target current value for each energization pattern, and a rotor stop position estimation unit for estimating a position at which the rotor stops.

An object of the present invention is to enable suppression of a leak current of an organic EL element while improving a conductivity of the organic EL element and suppressing an operation voltage thereof. An organic EL element is used which comprises at least a luminescent layer, a hole transport layer adjacent to a positive-electrode side of the luminescent layer, and an electron injection transport layer adjacent to a negative-electrode side of the luminescent layer, wherein a hole injection layer is provided between the hole transport layer and the positive electrode, and the conductivity of the hole injection layer continuously changes along a thickness direction of the hole injection layer.

A variable impedance composition according to one aspect of the present invention comprises a high electro-magnetic permeability powder in an amount from 10% to 85% of the weight of the variable impedance composition, and an insulation adhesive in an amount from 10% to 30% of the weight of the variable impedance composition. The incorporation of high electro-magnetic permeability powder including carbonyl metal, such as carbonyl iron or carbonyl nickel, in the variable impedance composition can not only suppress the overstress voltage, but also dampen the transient current. In contrast to the conventional electrostatic discharge (ESD) device, the relatively high electro-magnetic permeability carbonyl metal powder can reduce arcing as well as lower the trigger voltage of the device. The high electro-magnetic permeability characteristics can also absorb the undesirable electro-magnetic radiation that causes corruption of signal and loss of data.

An n-type region encloses an n-type well region is disclosed in which is disposed a high-side drive circuit. A high resistance polysilicon thin film configuring a resistive field plate structure of a high breakdown voltage junction termination region is disposed in spiral form on the n-type region. An OUT electrode, a ground electrode, and a Vcc1 electrode are disposed on the n-type region. The Vcc1 electrode is connected to the positive electrode of an auxiliary direct current power supply (a bootstrap capacitor). The OUT electrode is connected to the negative electrode of the auxiliary direct current power supply. One end portion (a second contact portion) of the high resistance polysilicon thin film is connected to the ground electrode, and the other end portion (a first contact portion) of the high resistance polysilicon thin film is connected to the OUT electrode.

JP920010105US125 A liquid crystal display driver for applying a voltage to liquid crystal cells forming an image display area includes a pulse generation circuit for generating a plurality of reference pulses in which pulse generation densities are weighted, a pulse select / synthesis circuit for generating a pulse string by selecting and synthesizing necessary reference pulses on the basis of digital input data and the reference pulses and an integration circuit (low pass filter) for integrating the pulse string generated by the pulse select / synthesis circuit to output an analog voltage for gamma correction.

The invention discloses an independent micro-grid layered coordinated control method based on different time scales. The method comprises the following steps of (1), according to the dynamic characteristics of voltage and frequency of an independent micro-grid system, dividing the fluctuation range of the voltage and frequency into three areas of A, B and C, wherein the area A represents that the deviation of the voltage and frequency is in a normal fluctuation range, the area B represents that the deviation of the voltage and frequency slightly exceeds the normal fluctuation range, and the area C represents that the deviation of the voltage and frequency seriously exceeds the normal fluctuation range; (2) monitoring and collecting the voltage U, the frequency f and the power P of the bus of the independent micro-grid, and determining the areas where the U and the f are located; (3) if the U and the f are located in the area A, keeping a storage battery energy storage system and a diesel generating set away from an adjustment process, if the U and the f are located in the area B, enabling the storage battery energy storage system in charge of primary control to participate in the adjustment process to achieve system power balance, and if the U and the f are located in the area C, enabling a secondary control diesel generator to participate in the adjustment process to achieve system power balance; (4) repeatedly collecting the U, the f and the P until the U and the f are determined to be located in the area A.

A manufacturing method of a semiconductor thin film decreases the number of and controls the direction of crystal grain boundaries. A first beam irradiated onto amorphous silicon produces a radial temperature gradient centered on a tip of a concave. This forms a crystal grain in the concave tip, which grows in both the beam width and length direction. After the second beam and on, growth is repeated using the crystal grain formed in the tip of the concave as the seed. This forms a band-form crystal grain with a wider than that of the conventional narrow-line beam, with the tip of the concave being the start point. Further, by setting the periphery of the concave pattern to be equal or less than the crystal grain diameter in the direction vertical to the beam scanning direction, it is possible to form the band-form crystal grain being lined continuously.

In a radiation imaging apparatus which comprises an envelope which has a first window for transmitting a radiation and is filled with an insulating liquid, a radiation tube in the envelope which has, at a position facing the first window, a second window for transmitting the radiation, and a shielding member, a solid insulating member is arranged between the shielding member and the inner wall of the envelope, an opening is formed at a position on the insulating member corresponding to the first window, and a shortest distance from the shielding member to the first window or the inner wall of the envelope through the opening of the insulating member without the insulating member is made longer than a shortest distance from the shielding member to the first window or the inner wall of the envelope through the insulating member, thereby improving withstand voltage performance without reducing an radiation amount.

A first inverter control unit includes a harmonic generation unit. The harmonic generation unit generates a harmonic voltage instruction having a phase opposite to a harmonic generated at a neutral point of a motor-generator when the motor-generator revolves, based on motor revolution number of the motor-generator. A PWM signal generation unit generates a signal based on a voltage instruction obtained by superimposing an AC voltage instruction from an AC output control unit and the harmonic voltage instruction from the harmonic generation unit onto each voltage instruction of U-phase, V-phase and W-phase from a conversion unit.