27 results about "Transistor count" patented technology

The present application relates to the field of artificial neuromorphics, and provides an artificial neuron circuit based on a volatile threshold switching device. A membrane potential generation circuit is used for generating different membrane potentials under different input currents and different external reset voltages; a slow variable generation circuit is used for generating a slow variable; a membrane potential reset circuit comprises a volatile threshold switching device and an external reset voltage excitation source; the external reset voltage excitation source is used for providing different external reset voltages, so that the membrane potential and the slow variable are changed, and a spiking behavior of biological neurons is simulated; and the volatile threshold switching device is used for realizing a membrane potential reset function. Compared with traditional CMOS-circuit-based neurons, the neuron circuit provided by the present application requires a greatly reduced number of transistors and reduced hardware and power consumption overhead, has the characteristics of simple structure, high flexibility and rich functions, and is beneficial to large-scale integration in a hardware pulse neural network.

A comparator circuit, comprising: a first pre-amplification stage, amplifying an input signal when in a comparison state, so as to generate a first output signal; a second pre-amplification stage, switching between a reset state and the comparison state on the basis of the first output signal, amplifying the first output signal when in the comparison state, so as to generate a second output signal, and providing positive feedback for the second output signal by means of a first positive feedback structure; and a latch stage, wherein in the reset state, an output end of the latch stage is reset to a second preset level on the basis of a clock signal, and in the comparison state, a second positive feedback structure and a third positive feedback structure are controlled to be on by means of the second output signal and the clock signal, so as to provide positive feedback to the output end. The comparator circuit reduces the number of transistors connected to the clock signal, thereby suppressing jittering of the clock signal, and effectively improving comparator precision.

The embodiment of the invention discloses a chip fault detection method, computer equipment and a storage medium, and the method comprises the steps: analyzing a circuit structure of a to-be-tested chip through a preset safety target based on the to-be-tested chip, and recognizing a fragile unit associated with the preset safety target; according to the fragile unit, an initial test vector set is generated, and the initial test vector set comprises a plurality of test vectors; determining the contribution degree of each test vector based on the number of transistors corresponding to the fragile units covered by each test vector; according to the contribution degree of each test vector, performing test vector combination on the plurality of test vectors to obtain a target test vector set; and inputting the test vectors in the target test vector set into the to-be-tested chip according to a preset rule combination for fault detection to obtain a fault detection result. According to the scheme, on the basis of not changing hardware, by optimizing the chip fault detection process, the fault detection efficiency is improved, and the high coverage rate is maintained.

This application provides a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit provided in this application can add 1 to and subtract 1 from an input logical value. On the basis of the ternary logic gate circuit, the ternary logic gate circuit is applied to a ternary logic circuit by using 27 single-variable functions of three-valued logic, so that a structure of the ternary logic circuit can be simplified, a quantity of transistors in the ternary logic circuit can be reduced, power consumption of the ternary logic circuit can be reduced, and computing efficiency of the ternary logic circuit can be improved.

The application discloses a kind of circuit, method and neural network hardware system for realizing non-monotonic activation function, belong to the technical field of neural network hardware circuit design, the circuit includes: first inverter, second inverter and logic processing unit;The input end of first inverter and second inverter is connected, as analog accumulation signal input end;First inverter and second inverter are respectively set first logic flip threshold voltage and second logic flip threshold voltage of unequal value;The two input ends of logic processing unit are respectively connected to the output end of first inverter and the output end of second inverter.The application realizes non-monotonic activation function under extremely simple circuit architecture by the combination of double threshold decision and logic processing, without analog-digital conversion module, with the advantages of less transistor number, low power consumption, easy to integrate.

This invention relates to the field of data storage technology, providing an 8.5T non-volatile random access memory (NVSRAM) cell, a memory, and a data storage method. It combines 6T SRAM cells connected to an isolation transistor to form an NVSRAM cell. This method uses fewer transistors, has a smaller chip area, and achieves high cell storage density. The data retrieval process of the NVSRAM cell does not require power-down of the SRAM cell, discharge of the data nodes, or power-on of the SRAM cell. The retrieval process is completed simply by writing data 0 to the data nodes QB of all SRAM cells, writing data 1 to the data nodes Q, and then opening the isolation transistor to write the data from the FLASH cell to the SRAM cell. This retrieval method is simple and efficient, simplifies the design of related peripheral circuits, and effectively reduces the chip manufacturing cost of NVSRAM.

The high-speed selective carry propagation adder circuit consists of a full adder that performs selective carry propagation in the critical path, rather than the conventional carry propagation method that limits operating speed. Instead of propagating the carry and using it for summation, it is proposed to propagate a selective carry in the critical path and use it for summation. As a result, the number of transistors required for the full adder cell is reduced, and high-speed operation and low power consumption are achieved by reducing parasitic resistance and capacitance. Furthermore, the proposed circuit design reduces the number of transistors required for a 1-bit full adder cell to 14 for static CMOS logic, 10 for transmission gate type, and 8 for pass transistor type. In addition, the proposed adder circuit provides a versatile and efficient solution for multi-bit adders in various logic schemes and is expected to have applications in various fields.

The present disclosure provides a touch substrate, a display device and a display system. By rearranging the layout of each transistor in the shift register, the number of transistors in the horizontal direction of the shift register is less than the number of transistors in the vertical direction, that is, the circuit of the shift register is designed in the vertical direction, which can reduce the size of the shift register in the horizontal direction, realize narrow frame design, and facilitate seamless splicing when applied to large-size panels.

The invention belongs to the technical field of semiconductors, and particularly provides a barrel type shifter based on ferroelectric field effect transistors, which comprises at least one alternative multiplexer, the alternative multiplexer comprises an N-type ferroelectric field effect transistor and a P-type ferroelectric field effect transistor, and the N-type ferroelectric field effect transistor is connected with the P-type ferroelectric field effect transistor. A drain electrode of the N-type ferroelectric field effect transistor and a source electrode of the P-type ferroelectric field effect transistor are connected to serve as an input end, a source electrode of the N-type ferroelectric field effect transistor and a drain electrode of the P-type ferroelectric field effect transistor are connected to serve as an output end, and grid electrodes of the N-type ferroelectric field effect transistor and the P-type ferroelectric field effect transistor are connected and connected with a master control signal; according to the invention, the adjustable threshold voltage and non-volatile storage characteristics of a ferroelectric field effect transistor (FeFET) are utilized, the left shift, right shift or cyclic shift function of any digit is realized in a single clock period, the number of transistors required in a traditional structure is effectively reduced, work under zero gate voltage is supported, and the circuit area and static power consumption are effectively reduced.

The present disclosure relates to a signal processing device, an imaging element, and an electronic apparatus that enable further characteristic improvement. This signal processing device is provided with a comparator in which a differential pair is configured from a first transistor group in which a first input signal is input to a gate terminal via a first capacitor, and a second transistor group in which a second input signal, the magnitude relationship of which with the first input signal is to be compared, is input to a gate terminal via a second capacitor. The signal processing device is configured such that the number of transistors in which the first input signal is input to the gate terminal, among the first transistor group, can be switched, and the number of transistors in which the second input signal is input to the gate terminal, among the second transistor group, can be switched. The present technology can be applied to, for example, a CMOS image sensor.

A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1st to Nth first shift registers that are configured to output 1st to Nth first scan signals to N number of scan lines, respectively. The second driving circuit includes 1st to Nth second shift registers that are configured to output 1st to Nth second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1st to Nth second shift registers is less than the number of transistors in each of the 1st to Nth first shift registers.

The invention discloses an ultrasonic sensor pixel circuit structure which comprises at least two pixel units, and each pixel unit comprises a piezoelectric material and an ultrasonic transceiving selector connected with a lower electrode of the piezoelectric material; the common circuit module comprises an ultrasonic transmitting and receiving controller, a source follower and a row and column selector; the ultrasonic transceiving selector of any pixel unit is connected to a common node of the common circuit module; the ultrasonic transceiving controller is connected with the common node and an external driving signal, a grid electrode of the source follower is connected with the common node, and an output end of the source follower is connected to the row and column selector; through the common circuit module of the plurality of pixel units, the number of transistors required by a single pixel is greatly reduced, more pixels can be accommodated under the same array area, and the pixel density of the sensor is improved, so that the resolution and the quality of sensing information such as fingerprint images are improved, and the power consumption is reduced.

The invention discloses an index and maximum value search unit circuit, array circuit and module for floating-point number calculation, and relates to the technical field of in-memory floating-point number calculation circuits. The invention discloses an index and maximum value searching unit circuit for floating-point number calculation. The index and maximum value searching unit circuit comprises N index and array units ISU1, j-ISUN, j, three phase inverters INV1j-INV3j and an either-or selector MUXj. ISU1, j-ISUN, j are distributed in an N * 1 matrix and share a calculation bit line CLj, a calculation bit line ORLj + 1 and a calculation bit line NANDLj + 1. The invention provides an index and maximum value search unit circuit for floating-point number calculation, which adopts a double-column parallel search architecture, determines the maximum value of a right column by using the maximum value found by a left column, can significantly reduce the search period, greatly improves the search speed, increases a small number of transistors, and avoids overlarge area overhead.

The present technology is related to transistor synthesis optimization during the physical design stage of EDA. Aspects of the present technology introduces new ways to restructure transistor-level netlists, such as by reducing transistor count, for digital circuit designs based on the enumeration of “don't cares” of internal nets. One aspect of the present technology includes connecting internal nets with the same truth table up to don't cares without changing the functionality of the entire circuit. With an additional connection in the netlist, optimization opportunities can be identified that may remove transistors and / or improve placement, routing, and / or timing metrics. Furthermore, optimization opportunities may be further increased by (pre)computing satisfiability don't cares at the inputs of the netlist and observability don't cares at the outputs of the netlist from the environment.

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

To provide a semiconductor device that can reduce power consumption and has a small number of transistors. [Solution] One of the source and drain is electrically connected to the first wiring, and the source and drain The other end of the rain is electrically connected to the second wiring, and the first transistor is connected to the source and drain. One end of the input is electrically connected to the first wiring, and the gate is electrically connected to the gate of the first transistor. A second transistor is electrically connected, and one of its electrodes is electrically connected to a third wire. The other electrode is a capacitance electrically connected to the other source and drain of the second transistor. It has an element and

The present disclosure provides a display base plate and a display device.The drive circuit comprises a drive control signal generation circuit and a multiple output circuit; the multiple output circuit comprises N stages of output sub-circuits, where N is an integer greater than 1; the nth output sub-circuit is electrically connected to a drive control signal output, a control voltage line, an nth control node, an nth output clock signal line, and an nth drive signal output, wherein the nth output sub-circuit is designed to control the potential of the nth control node under control of a control voltage according to the drive control signal, and to control the nth output clock signal line under control of the potential of the nth control node such that it provides an nth output clock signal to the nth drive signal output; where n is a positive integer less than or equal to N.With the present disclosure, multiple rows of gate lines can be driven by a single drive circuit, effectively reducing the number of transistors used in the drive circuit and facilitating the realization of narrow margins.

The application provides a gate driving circuit, and belongs to the technical field of display. A pull-up control module outputs an n-level control signal according to an n-4-level trigger signal. A first end of a first transistor obtains a clock signal, and a second end of the first transistor obtains a first local clock signal. The n-4-level trigger signal is opposite to the clock signal CLK. A first end of a second transistor is connected with the pull-up control module and obtains the n-level control signal. A third end of the first transistor outputs a first reverse signal, and a third end of the second transistor obtains a first reference low voltage. Through the first transistor and the second transistor, the potential of the n-level control signal is opposite to the potential of the first reverse signal under the regulation of the clock signal, the first local clock signal and the n-level control signal, the function of the inverter module is realized, the number of transistors is reduced, and the problem that the frame of the display panel is large due to the large number of transistors in the inverter module of the traditional circuit is solved.

A compute engine for BitNet b1.58-style inference employs arrays of ultra-simple processing elements that implement ternary weights using sign selection and conditional accumulation rather than a conventional multiplier. Each processing element stores a weight encoding +1, 0, or −1, selects a non-inverted activation, a zero, or an inverted activation accordingly, and updates a saturating accumulator while skipping accumulator clocking on zero weights. The processing elements are arranged for deterministic systolic dataflow across an all-silicon domain, enabling massive replication with low transistor count per element. Optional tiles interface via first-in first-out buffers in lieu of caches to preserve timing predictability. The approach reduces area and power while sustaining multi-gigahertz operation suited to transformer inference.

The application discloses an arithmetic operation unit of independent carry register, and belongs to the technical field of computer processor design. A 64-base column structure is adopted, 8 bits of each column are equal to 6 data bits plus 2 carry bits, and 8 columns are simultaneously operated through a single 64-bit adder. The carry is stored in the independent register with the high 2 bits in the column, the carry register in the column embeds the carry in the data column, and the serial carry chain is eliminated. The parallel adder array uses 8 6-bit adders to work simultaneously, and there is no cascading dependence. A carry delay propagation circuit supports a configurable threshold, and the carry is temporarily not carried out during the operation process, and is processed in batches when needed. Compared with the traditional serial carry chain, the delay of the application is reduced by 8 times, the complexity is reduced from O(64) to O(8), the number of transistors is reduced by 77%, from 2300 to 532, the power consumption is reduced by 87.5%, the gate circuit flip is reduced from 64 levels to 8 levels, and parallel operation is supported throughout the process. The application is realized by using Verilog HDL, can be adapted to FPGA and ASIC, can integrate the existing CPU architecture, does not need to change the instruction set, the compiler is automatically optimized, and the program does not need to be adjusted.

Embodiments of the present application provide a pixel driving device and a display panel, wherein the pixel driving device comprises: a first driving circuit comprising a first pull-up module, a first output module, a first pull-down module and a first reset module formed by a plurality of first transistors, the first driving circuit having a first pull-up node and a first pull-down node; and a second driving circuit comprising a second pull-up module, a second output module and a second reset module formed by a plurality of second transistors, the number of the second transistors being less than the number of the first transistors; wherein the second driving circuit has a second pull-down node coupled to the first pull-down node, or the second driving circuit has a second pull-up node coupled to the first pull-up node. According to the technology of the present application, the number of transistors of the pixel driving circuit can be reduced, thereby reducing the occupation of the pixel driving circuit in the horizontal space, and further meeting the display requirement of narrow frame.

This invention relates to the field of display technology, and specifically discloses an array substrate, a driving method for pixel circuits, and a display panel. The array substrate includes at least one pixel circuit. The pixel circuit includes a first storage module connected between a first control terminal and a first terminal of a driving module; a second storage module connected between a second control terminal and the first terminal of the driving module; a writing module transmitting a data signal or a first power signal to the first control terminal of the driving module according to a first scan signal; a first initialization module turning on or off the connection between the second control terminal of the driving module and a first initialization signal line according to a first switch signal; and a second initialization module turning on or off the connection between the second terminal of the driving module and a second initialization signal line according to a second switch signal. The pixel circuit design on the above-mentioned array substrate uses a small number of transistors, enabling ultra-high PPI display arrangements when applied to display products.

A high speed selective carry propagation adder circuit includes a full adder that performs selective carry propagation in a critical path rather than a conventional way of the carry propagation method that limits the computing speed. Instead of propagating the carry and using it for the sum calculation, we propose propagating the selective carry in the critical path and using it for the sum calculation. As a result, fewer transistors are required in the full adder cell, resulting in faster performance and less power consumption due to reduced parasitic resistance and capacitance. In addition, the proposed circuit design reduces the transistor count required for a one-bit full adder cell to 14 transistors in static CMOS logic, 10 transistors in pass gates, and 8 transistors in pass transistor logic types. In addition, the adder circuit provides a universal and efficient technical scheme for multi-bit adders of various logic types, and has potential application in various fields.

The invention provides a method and a device for counting the number of transistors in a chip. The method for counting the number of the transistors in the chip comprises the steps of determining the number of the transistors of various types of standard units in a target chip; a functional module hierarchical structure in the target chip is obtained, the upper layer and the lower layer of the functional module hierarchical structure have a father-son relationship, and each functional module in the last layer is composed of a standard unit; determining the number of transistors of the last layer of function module according to the number of transistors corresponding to the type of the standard unit of the last layer of function module; and traversing the number of transistors of each layer of function module upwards according to the hierarchical father-son relationship of the hierarchical structure of the function module and the number of transistors of the last layer of function module until the number of transistors of the target chip is determined. According to the method for counting the number of the transistors in the chip, the accuracy of counting the number of the transistors in the target chip is improved.

A electronic device includes a controller and a power supply. The controller stores a table including gate signal frequencies and numbers of power transistors for plural operations, and based on the table and an operation request to perform an operation, outputs a power control signal including one or both of gate signal frequency for the operation and a number of power transistors for the operation. The power supply includes plural power transistors that receive gate signals. The power supply, based on the power control signal, generates one or more gate signals input to one or more power transistor among the plural power transistors, and, based on turn-on of the one or more power transistors, generates a load supply voltage based on a system supply voltage.

This disclosure provides a carry compression circuit, a chip, and an electronic device. The carry compression circuit includes a first selection module and a second selection module. The first selection module is used to perform XOR processing on a first input signal and a second input signal to obtain a first XOR result, select a first carry output signal from the first input signal and a third input signal based on the first XOR result, and output it; and determine an intermediate processing result based on the first XOR result and the third input signal and send it to the second selection module. The second selection module is used to perform XOR processing on the intermediate processing result and a fourth input signal to obtain a second XOR result, and determine a second carry output signal and an XOR output signal based on the second XOR result and the carry input signal, and output them. Embodiments of this disclosure can reduce the number of transistors.

A non-transitory computer-readable medium that includes computer-executable instructions for carrying out a method (of expanding a set of standard cells which comprise a library) including: identifying ad hoc groups of elementary standard cells which are recurrent (in a population of one or more layout diagrams) and each of which, as a whole, having a first number of transistors and a second number of logic gates; and selecting one of the ad hoc groups to provide a selected logical function which is representable as a Boolean expression; generating one or more macro standard cells each of which, as a whole, having a third number of components (representing transistors or logic gates in a context of the first or second numbers) which is smaller than the first number or the second number; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells.