56 results about "Transistor count" patented technology

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

Methods and systems for optimized pruning and structuring of trained convolutional neural networks are provided. In some methods, the weight matrices of one or more convolutional layers of a trained CNN model are profiled and a weight distribution is determined. Based on this, a pruning threshold may be determined, and utilized to prune weights of the matrices whose values are below the threshold. This may be iteratively repeated until an optimal tradeoff of model reduction vs accuracy is achieved. Resulting pruned models may be utilized in resource constrained applications, such as in edge or IoT devices, or may be utilized to develop optimized, custom circuits or chips with reduced transistor count that perform the classification task of the trained CNN model.

A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1st to Nth first shift registers that are configured to output 1st to Nth first scan signals to N number of scan lines, respectively. The second driving circuit includes 1st to Nth second shift registers that are configured to output 1st to Nth second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1st to Nth second shift registers is less than the number of transistors in each of the 1st to Nth first shift registers.

The utility model discloses a storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistors. The storage and calculation integrated majority voting logic gate circuit comprises an input module, an operation module, a discharge module and an output module, the input module receives three voltage signals and transmits the three voltage signals to the operation module according to a time sequence; the operation module comprises a ferroelectric field effect transistor, formation and damage of a conducting channel of the ferroelectric field effect transistor are directionally changed according to voltage signals received by a grid electrode and a source electrode, a nonvolatile operation relation with an external voltage signal as input and on-off of an internal channel as output is established, a logic input variable form is unified, and majority voting logic operation is executed. The discharging module adjusts a voltage signal of the operation module in a reading stage to prevent misreading; the output module accurately reads a nonvolatile operation result as a voltage signal; the circuit has the advantages that the storable majority voting logic function can be realized with a small number of transistors, the logic input variable form is unified, and the operation cascading capability and the circuit expandability are improved.

The invention relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, in the semiconductor device, at least two first grids and at least two first active regions are arranged in a crossed manner, a second active region is positioned between the adjacent first active regions, and a second grid is positioned on the second active region; when at least four transistors are formed on the semiconductor device, a fifth transistor is formed on the second active region and the second grid electrode. According to the arrangement, the number of the transistors is increased while the structure of the semiconductor device is not changed, the integration level of the semiconductor device is increased, and the performance of the semiconductor device is further improved.

The invention provides a liquid crystal display device which comprises a plurality of pixels, a plurality of gate lines and a plurality of data lines, each pixel comprises a main pixel and a secondary pixel and only comprises two transistors, the first transistor is electrically connected with the secondary pixel, and the second transistor is electrically connected with the main pixel. In the first embodiment, one group of gate lines comprises a first gate line and a second gate line which are electrically connected with the first transistor and the second transistor respectively, and different gray-scale signals are input to the main pixel and the secondary pixel by controlling the switching time sequence of gate line signals and the input time sequence of data line signals. In the second embodiment, one group of data lines comprises a first data line and a second data line which are electrically connected with the secondary pixels and the main pixels respectively, and the two data lines are controlled to input different gray-scale signals to the main pixels and the secondary pixels at the same time, so that different gray-scale signals are input to the main pixels and the secondary pixels. According to the invention, a common electrode is removed and the number of transistors is reduced, so that the aperture opening ratio and the penetration rate are improved.

The invention provides a back power supply chip stacking structure and a preparation method thereof, the chip stacking structure comprises two chips which are bonded up and down, the two chips realize signal transmission through signal connection layers which are bonded with each other, and the two chips are connected with each other through a power rail and an embedded power layer. Only by forming the metal interconnection layer on the back of the first chip as the back power supply layer, the transistors of the upper chip and the lower chip can be powered, and transmission of electric signals is achieved. By means of the stacking design, the chip stacking structure can achieve the double number of transistors under the same area, for example, only a 14 nm manufacturing process can be used, the upper and lower transistor stacking method is combined, the number of transistors under a 7 nm manufacturing process is achieved, the same performance is achieved, and therefore the process cost is saved. In addition, the second chip bonded with the first chip also serves as a temporary slide glass, so that the temporary slide glass does not need to be additionally provided, and the manufacturing cost is further reduced.

The present application relates to the field of artificial neuromorphics, and provides an artificial neuron circuit based on a volatile threshold switching device. A membrane potential generation circuit is used for generating different membrane potentials under different input currents and different external reset voltages; a slow variable generation circuit is used for generating a slow variable; a membrane potential reset circuit comprises a volatile threshold switching device and an external reset voltage excitation source; the external reset voltage excitation source is used for providing different external reset voltages, so that the membrane potential and the slow variable are changed, and a spiking behavior of biological neurons is simulated; and the volatile threshold switching device is used for realizing a membrane potential reset function. Compared with traditional CMOS-circuit-based neurons, the neuron circuit provided by the present application requires a greatly reduced number of transistors and reduced hardware and power consumption overhead, has the characteristics of simple structure, high flexibility and rich functions, and is beneficial to large-scale integration in a hardware pulse neural network.

A data register unit, a SAR ADC and an electronic device are disclosed. The data register unit comprises: a first high-speed flip-flop; a second high-speed flip-flop; and a first logic gate, wherein the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, which comprises: a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate. The data register unit of the present disclosure is composed of a high-speed flip-flop circuit with a very simple structure and suitable for fast operation. In a further embodiment, the high-speed flip-flop circuit can combine the bit pulse to realize the capacitor switching based on the comparison result. This increases the operation speed of the SAR ADC while significantly reducing the number of transistors required to implement the EMCS logic.

A method for implementing a logic circuit employing a combination of binary adders of different lengths having summation and carry outputs and AND gates, comprising the steps of replacing at least one known CMOS implemented binary adder with an improved binary adder consisting of a logic block for performing summation between binary inputs of the logic block; a restoration block, connected between the output of the logic block and the output of the binary adder circuit, for compensating for voltage level losses when the output is in a high logic state or low logic state. The at least one CMOS AND gate is replaced with a high Fan-in AND gate being above a predetermined threshold, by an improved AND gate consisting of a logic block for performing an AND operation between binary inputs of the logic block; a restoration block, connected between the output of the logic block and the output of the AND gate, for compensating for voltage level losses when the output being in a high logic state or low logic state.

A comparator circuit, comprising: a first pre-amplification stage, amplifying an input signal when in a comparison state, so as to generate a first output signal; a second pre-amplification stage, switching between a reset state and the comparison state on the basis of the first output signal, amplifying the first output signal when in the comparison state, so as to generate a second output signal, and providing positive feedback for the second output signal by means of a first positive feedback structure; and a latch stage, wherein in the reset state, an output end of the latch stage is reset to a second preset level on the basis of a clock signal, and in the comparison state, a second positive feedback structure and a third positive feedback structure are controlled to be on by means of the second output signal and the clock signal, so as to provide positive feedback to the output end. The comparator circuit reduces the number of transistors connected to the clock signal, thereby suppressing jittering of the clock signal, and effectively improving comparator precision.

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and / or minority gates. The majority and / or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and / or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and / or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

The embodiment of the invention discloses a chip fault detection method, computer equipment and a storage medium, and the method comprises the steps: analyzing a circuit structure of a to-be-tested chip through a preset safety target based on the to-be-tested chip, and recognizing a fragile unit associated with the preset safety target; according to the fragile unit, an initial test vector set is generated, and the initial test vector set comprises a plurality of test vectors; determining the contribution degree of each test vector based on the number of transistors corresponding to the fragile units covered by each test vector; according to the contribution degree of each test vector, performing test vector combination on the plurality of test vectors to obtain a target test vector set; and inputting the test vectors in the target test vector set into the to-be-tested chip according to a preset rule combination for fault detection to obtain a fault detection result. According to the scheme, on the basis of not changing hardware, by optimizing the chip fault detection process, the fault detection efficiency is improved, and the high coverage rate is maintained.

This application provides a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit provided in this application can add 1 to and subtract 1 from an input logical value. On the basis of the ternary logic gate circuit, the ternary logic gate circuit is applied to a ternary logic circuit by using 27 single-variable functions of three-valued logic, so that a structure of the ternary logic circuit can be simplified, a quantity of transistors in the ternary logic circuit can be reduced, power consumption of the ternary logic circuit can be reduced, and computing efficiency of the ternary logic circuit can be improved.

The present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure comprises two chips bonded together, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, in combination with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer as a back power supply layer on the back of the first chip, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can achieve twice the number of transistors in the same area. For example, only a 14nm process can be used to achieve the number of transistors under a 7nm process. At the same time, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, which further reduces the production cost. In addition, the process of making the back power supply channel is moved forward, so that the preparation process is carried out sequentially from bottom to top, and the process rationality is better.

The application discloses a kind of circuit, method and neural network hardware system for realizing non-monotonic activation function, belong to the technical field of neural network hardware circuit design, the circuit includes: first inverter, second inverter and logic processing unit;The input end of first inverter and second inverter is connected, as analog accumulation signal input end;First inverter and second inverter are respectively set first logic flip threshold voltage and second logic flip threshold voltage of unequal value;The two input ends of logic processing unit are respectively connected to the output end of first inverter and the output end of second inverter.The application realizes non-monotonic activation function under extremely simple circuit architecture by the combination of double threshold decision and logic processing, without analog-digital conversion module, with the advantages of less transistor number, low power consumption, easy to integrate.

A voltage generator includes a temperature-dependent voltage generator and a reference voltage node. The temperature-dependent voltage generator generates a voltage that increases with temperature and includes a first transistor stack and a second transistor stack. Each of the first transistor stack and the second transistor stack has a predetermined number of transistors. The number of the transistors of the second transistor stack is greater than the number of the transistors of the first transistor stack. The reference voltage node is connected to the temperature-dependent voltage generator and provides a reference voltage substantially independent of temperature. A method for generating the temperature-independent reference voltage is also disclosed.

Disclosed in the present invention are a highly energy-efficient CAM based on a single FeFET and an operating method thereof, which relate to a design of an FeFET-based memory suitable for low power consumption and high performance. A brand-new design of a CAM cell based on the single FeFET is achieved by fully utilizing the storage characteristics of the FeFET, so that the number of transistors is saved, the search energy consumption is reduced, and the nonvolatility of data storage is obtained. The present invention utilizes a 2T-1FeFET structure, and combines the advantages of the FeFET and CMOS. Without reducing performance, only one FeFET is utilized to implement a less area overhead and a lower energy consumption compared with a traditional CMOS-based CAM, and non-volatility is achieved.

This invention relates to the field of data storage technology, providing an 8.5T non-volatile random access memory (NVSRAM) cell, a memory, and a data storage method. It combines 6T SRAM cells connected to an isolation transistor to form an NVSRAM cell. This method uses fewer transistors, has a smaller chip area, and achieves high cell storage density. The data retrieval process of the NVSRAM cell does not require power-down of the SRAM cell, discharge of the data nodes, or power-on of the SRAM cell. The retrieval process is completed simply by writing data 0 to the data nodes QB of all SRAM cells, writing data 1 to the data nodes Q, and then opening the isolation transistor to write the data from the FLASH cell to the SRAM cell. This retrieval method is simple and efficient, simplifies the design of related peripheral circuits, and effectively reduces the chip manufacturing cost of NVSRAM.

The high-speed selective carry propagation adder circuit consists of a full adder that performs selective carry propagation in the critical path, rather than the conventional carry propagation method that limits operating speed. Instead of propagating the carry and using it for summation, it is proposed to propagate a selective carry in the critical path and use it for summation. As a result, the number of transistors required for the full adder cell is reduced, and high-speed operation and low power consumption are achieved by reducing parasitic resistance and capacitance. Furthermore, the proposed circuit design reduces the number of transistors required for a 1-bit full adder cell to 14 for static CMOS logic, 10 for transmission gate type, and 8 for pass transistor type. In addition, the proposed adder circuit provides a versatile and efficient solution for multi-bit adders in various logic schemes and is expected to have applications in various fields.

The present disclosure provides a touch substrate, a display device and a display system. By rearranging the layout of each transistor in the shift register, the number of transistors in the horizontal direction of the shift register is less than the number of transistors in the vertical direction, that is, the circuit of the shift register is designed in the vertical direction, which can reduce the size of the shift register in the horizontal direction, realize narrow frame design, and facilitate seamless splicing when applied to large-size panels.

An array substrate is provided. The array substrate includes a plurality of first subpixels in a first region and a plurality of second subpixels in a second region. The plurality of first subpixels include a plurality of first pixel driving circuits. The plurality of second subpixels include a plurality of second pixel driving circuits. A respective first pixel driving circuit of the plurality of first pixel driving circuits includes a smaller number of transistors than a respective second pixel driving circuit of the plurality of second pixel driving circuits. The first region has a light transmittance higher than the second region, and a subpixel density same as the second region.

The invention belongs to the technical field of semiconductors, and particularly provides a barrel type shifter based on ferroelectric field effect transistors, which comprises at least one alternative multiplexer, the alternative multiplexer comprises an N-type ferroelectric field effect transistor and a P-type ferroelectric field effect transistor, and the N-type ferroelectric field effect transistor is connected with the P-type ferroelectric field effect transistor. A drain electrode of the N-type ferroelectric field effect transistor and a source electrode of the P-type ferroelectric field effect transistor are connected to serve as an input end, a source electrode of the N-type ferroelectric field effect transistor and a drain electrode of the P-type ferroelectric field effect transistor are connected to serve as an output end, and grid electrodes of the N-type ferroelectric field effect transistor and the P-type ferroelectric field effect transistor are connected and connected with a master control signal; according to the invention, the adjustable threshold voltage and non-volatile storage characteristics of a ferroelectric field effect transistor (FeFET) are utilized, the left shift, right shift or cyclic shift function of any digit is realized in a single clock period, the number of transistors required in a traditional structure is effectively reduced, work under zero gate voltage is supported, and the circuit area and static power consumption are effectively reduced.

The present disclosure relates to a signal processing device, an imaging element, and an electronic apparatus that enable further characteristic improvement. This signal processing device is provided with a comparator in which a differential pair is configured from a first transistor group in which a first input signal is input to a gate terminal via a first capacitor, and a second transistor group in which a second input signal, the magnitude relationship of which with the first input signal is to be compared, is input to a gate terminal via a second capacitor. The signal processing device is configured such that the number of transistors in which the first input signal is input to the gate terminal, among the first transistor group, can be switched, and the number of transistors in which the second input signal is input to the gate terminal, among the second transistor group, can be switched. The present technology can be applied to, for example, a CMOS image sensor.

A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1st to Nth first shift registers that are configured to output 1st to Nth first scan signals to N number of scan lines, respectively. The second driving circuit includes 1st to Nth second shift registers that are configured to output 1st to Nth second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1st to Nth second shift registers is less than the number of transistors in each of the 1st to Nth first shift registers.

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

The invention discloses an ultrasonic sensor pixel circuit structure which comprises at least two pixel units, and each pixel unit comprises a piezoelectric material and an ultrasonic transceiving selector connected with a lower electrode of the piezoelectric material; the common circuit module comprises an ultrasonic transmitting and receiving controller, a source follower and a row and column selector; the ultrasonic transceiving selector of any pixel unit is connected to a common node of the common circuit module; the ultrasonic transceiving controller is connected with the common node and an external driving signal, a grid electrode of the source follower is connected with the common node, and an output end of the source follower is connected to the row and column selector; through the common circuit module of the plurality of pixel units, the number of transistors required by a single pixel is greatly reduced, more pixels can be accommodated under the same array area, and the pixel density of the sensor is improved, so that the resolution and the quality of sensing information such as fingerprint images are improved, and the power consumption is reduced.

The invention discloses an index and maximum value search unit circuit, array circuit and module for floating-point number calculation, and relates to the technical field of in-memory floating-point number calculation circuits. The invention discloses an index and maximum value searching unit circuit for floating-point number calculation. The index and maximum value searching unit circuit comprises N index and array units ISU1, j-ISUN, j, three phase inverters INV1j-INV3j and an either-or selector MUXj. ISU1, j-ISUN, j are distributed in an N * 1 matrix and share a calculation bit line CLj, a calculation bit line ORLj + 1 and a calculation bit line NANDLj + 1. The invention provides an index and maximum value search unit circuit for floating-point number calculation, which adopts a double-column parallel search architecture, determines the maximum value of a right column by using the maximum value found by a left column, can significantly reduce the search period, greatly improves the search speed, increases a small number of transistors, and avoids overlarge area overhead.

The invention discloses a power amplifier, relates to the technical field of base stations, and aims to solve the problem of low efficiency of a traditional power amplifier in an output power backoff region in the prior art. The power amplifier comprises a driving amplifier, a power divider and an inversion Doherty amplifier, the inversion Doherty amplifier comprises a carrier amplifier and a peak amplifier, the driving amplifier receives radio frequency signals and is connected with the power divider, a first output end of the power divider is connected with the carrier amplifier, a second output end of the power divider is connected with the peak amplifier, and a third output end of the power divider is connected with the peak amplifier. The first output end of the power divider is connected with the carrier amplifier, the second output end of the power divider is connected with the peak amplifier, the carrier amplifier comprises a first transistor amplification module, the peak amplifier comprises a second transistor amplification module, and the ratio of the number of transistors of the first transistor amplification module to the number of transistors of the second transistor amplification module is a preset ratio. The preset ratio is less than 1.