Subunit, MAC array and bit width reconfigurable analog-digital hybrid in-memory calculation module

Abstract

The invention relates to a subunit for analog-digital hybrid in-memory calculation for 1-bit multiplication, where only nine transistors are required. On this basis, it is provided that a plurality ofsubunits share a calculation capacitor and the transistors to form one calculation unit, so that the number of the transistors averaged from the subunits is close to eight. Then an MAC array is provided for multiply-add calculation, and comprises a plurality of calculation units, and the subunits in each unit are activated in a time division multiplexing mode. Furthermore, a differential system of the MAC array is provided, and the fault-tolerant capability of calculation is improved. Furthermore, the invention provides an analog-digital hybrid operation module used in the memory, which digitalizes the parallel analog output of the MAC array and performs the operation in other digital domains. The analog-to-digital conversion module in the operation module makes full use of the capacitorof the MAC array, so that the area of the operation module can be reduced, and the operation error can also be reduced. Furthermore, the invention provides a method for saving the energy consumption of the analog-to-digital conversion module by fully utilizing the data sparsity.

Description

technical field [0001] The present invention relates to the field of modular-digital hybrid in-memory computing, and more specifically, relates to a subunit, a MAC array, and a modulus-digital hybrid in-memory computing module with reconfigurable bit width. Background technique [0002] Currently, emerging edge applications such as existing mobile and IoT require high energy efficiency and high computing speed per unit area. High energy efficiency means longer battery life, and high operation rate per unit area means reduced area at a specified operation rate, thereby reducing costs. Nowadays, feed-forward inference calculations in Deep Neural Network (DNN) are dominated by Multiply-And-Accumulate (MAC) calculations, which require high energy efficiency and low-area implementation of MAC calculations while reducing pending Data transfer volume. Traditional digital integrated circuit implementation of MAC has the advantages of strong anti-noise ability, high precision, good...

AI Technical Summary

Problems solved by technology

The disadvantages of the SRAM in paper 4 are: (1) Each 1-bit computing SRAM cell has 10 transistors

The scheme of the article adopts a maximum occupancy of 2 N -1 (N is the ADC resolution) step-based ramp-based ADC that converges reduces the speed of analog-to-digital conversion, resulting in lower computational throughput; (5) the input of the array uses an additional DAC circuit to convert the input data x in (Usually a feature map) Converting from a digital representation to an analog representation, the non-ideal nature of the DAC circuit results in more loss of precision as well as area and energy overhead

[0006] To sum up, in the calculation process of the neural network, the calculation unit for 1-bit multiplication in the MAC array in the prior art uses more transistors; the capacitor for storing the multiplication result for accumulation is in one-to-one correspondence with the storage unit, that is, the storage unit The number of capacitors is the same as the number of capacitors, and the capacitors are generally much larger than the SRAM unit, especially in the advanced process, which will cause the MAC array to occupy a large area; at the same time, there is unconditional drive of transistors in the multiply-add operation, resulting in poor computing energy efficiency. High; in addition, the high calculation error rate leads to limited applicable scenarios, etc.

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