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480 results about "Partition of unity" patented technology

In mathematics, a partition of unity of a topological space X is a set R of continuous functions from X to the unit interval [0,1] such that for every point, x∈X, there is a neighbourhood of x where all but a finite number of the functions of R are 0, and the sum of all the function values at x is 1, i.e., ∑ρ∈Rρ(x)=1. Partitions of unity are useful because they often allow one to extend local constructions to the whole space.

Graph-based semi-supervised high-spectral remote sensing image classification method

The invention relates to a graph-based semi-supervised high-spectral remote sensing image classification method. The method comprises the following steps: extracting the features of an input image; randomly sampling M points from an unlabeled sample, constructing a set S with L marked points, constructing a set R with the rest of the points; calculating K adjacent points of the points in the sets S and R in the set S by use of a class probability distance; constructing two sparse matrixes WSS and WSR by a linear representation method; using label propagation to obtain a label function F<*><S>, and calculating the label prediction function F<*><R> of the sample points in the set R to determine the labels of all the pixel points of the input image. According to the method, the adjacent points of the sample points can be calculated by use of the class probability distance, and the accurate classification of high-spectral images can be achieved by utilizing semi-supervised conduction, thus the calculation complexity is greatly reduced; in addition, the problem that the graph-based semi-supervised learning algorithm can not be used for large-scale data processing is solved, and the calculation efficiency can be improved by at least 20-50 times within the per unit time when the method provided by the invention is used, and the visual effects of the classified result graphs are good.
Owner:XIDIAN UNIV

Hardware architecture of binary weight convolution neural network accelerator and calculation process thereof

The invention discloses the hardware architecture of a binary weight convolution neural network accelerator and a calculation process thereof. The hardware architecture comprises three double-ended on-chip static random access memories which are used for buffering the binary weight of input neurons and a convolution layer, four convolution processing units capable of controlling calculation parts to complete major convolution calculation operation according to the calculation process, a feature map accumulation unit and a convolutional accumulation array. The feature map accumulation unit and the convolutional accumulation array are used for further processing the operation result of the convolution processing units to acquire a final correct output neuron value. The entire design exchanges data with an off-chip memory via a dynamic random access memory interface. In addition to the hardware architecture, the invention further provides the detailed calculation process which optimizes the hardware architecture and uses four lines of input feature map as a complete calculation unit. According to the invention, input data are reused to the greatest extent; the access of the off-chip memory is eliminated as much as possible; the power consumption of the deep binary convolution neural network calculation can be effectively reduced; a deep network is supported; and the scheme provided by the invention is a reasonable scheme which can be applied to an embedded system of visual application.
Owner:南京风兴科技有限公司

Method and apparatus for designing and manufacturing electronic circuits subject to process variations

Methods and apparatus are described in which, at design-time a thorough analysis and exploration is performed to represent a multi-objective “optimal” trade-off point or points, e.g. on Pareto curves, for the relevant cost (C) and constraint criteria. More formally, the trade-off points may e.g. be positions on a hyper-surface in an N-dimensional Pareto search space. The axes represent the relevant cost (C), quality cost (Q) and restriction (R) criteria. Each of these working points is determined by positions for the system operation (determined during the design-time mapping) for a selected set of decision knobs (e.g. the way data are organized in a memory hierarchy). The C-Q-R values are determined based on design-time models that then have to be “average-case” values in order to avoid a too worst-case characterisation. At processing time, first a run-time BIST manager performs a functional correctness test, i.e. checks all the modules based on stored self-test sequences and “equivalence checker” hardware. All units that fail are deactivated (so that they cannot consume any power any more) and with a flag the run-time trade-off controllers, e.g. Pareto controllers, are informed that these units are not available any more for the calibration or the mapping. At processing time, also a set of representative working points are “triggered” by an on-chip trade-off calibration manager, e.g. a Pareto calibration manager, that controls a set of monitors which measure the actual C-Q-R values and that calibrates the working points to their actual values. Especially timing monitors require a careful design because correctly calibrated absolute time scales have to be monitored.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)

Electromagnetic transient simulation method of electric system based on matrix exponential

An electromagnetic transient simulation method of an electric system based on a matrix exponential comprises the steps of establishing an electromagnetic transient simulation model, as shown in the specification, of the system to be studied under a state analysis frame, starting a simulation program after setting simulation step sizes delta t and relevant simulation parameters, forming an augmented state matrix with an excitation source g(t) of the current moment, each derivative information and a state matrix A in each simulation step size, solving the matrix exponential e<delta t A> by a Scaling and Squaring algorithm, performing matrix vector multiplication on an augmented state vector formed with a state variable vector x(t) and a p-dimensional unit vector, taking a result as a state variable of the current moment, obtaining an output vector y(t) through an output equation, writing into an output file, simulating and boosting one step size, and judging a short circuit, an open circuit and switch motion firstly in the next simulation step size. The method can achieve electromagnetic transient modeling simulation of the electric system with a complicated structure, asymmetric height, and the model having the characteristic of rigidity.
Owner:ELECTRIC POWER RESEARCH INSTITUTE, CHINA SOUTHERN POWER GRID CO LTD +1

Quasi-cyclic low density parity check code (LDPC) construction method and device based on protographs

The invention discloses a quasi-cyclic low density parity check code (LDPC) construction method and a device based on protographs. The protographs are expanded for two times in the construction method. A first expansion time L1 is smaller. A correcting progressive edge growth (PEG) algorithm is adopted to remove multiple edges of protographs. The girths of codes which are expanded are increased. A second expansion time is L2 and a cyclic shift offset is selected for connection which is established in the first expansion. Each connection corresponds to a unit cyclic matrix, wherein the size of the unit cyclic matrix is L2 * L2. The method references a local optimization idea of the PEG algorithm to construct a basis matrix of the quasi-cyclic LDPC code. The connection is established between each row of variable nodes and checking nodes and is confirmed in corresponding cyclic shift offset process. According to the correcting PEG algorithm, new rings formed in the basis matrix caused by the newly established connection are gone through. The fact that expansion factors A of the rings are larger than one is guaranteed. Thus, the rings with length of four are avoided. The number of short rings is reduced. The short rings which are small in connectivity emerge in a checking matrix are avoided by utilizing an ACE multiplication principle.
Owner:PEKING UNIV

Abstract convex lower-bound estimation based protein structure prediction method

Disclosed is an abstract convex lower-bound estimation based protein structure prediction method. The method includes: firstly, aiming for high-dimensional conformational spatial sampling problems for proteins, adopting a series of transform methods to transform an ECEPP / 3 force field model into an increasing radial convex function in unit simple constraint conditions; secondly, based on an abstract convex theory, proving and analyzing to give out a supporting hyperplane set of the increasing radial convex function; thirdly, constructing a lower-bound underestimate supporting plane on the basis of population minimization conformation subdifferential knowledge under a differential evolution population algorithm framework; fourthly, by the aid of a quick underestimate supporting plane extreme point enumeration method, gradually decreasing a conformational sampling space to improve sampling efficiency; fifthly, utilizing the lower-bound underestimate supporting plane for quickly and cheaply estimating an energy value of an original potential model to effectively decrease evaluation times of a potential model objective function; finally, verifying effectiveness of the method by methionine-enkephalin (TYR1-GLY2-GLY3-PHE4-MET5) conformational spatial optimization examples. The abstract convex lower-bound estimation based protein structure prediction method is high in reliability, low in complexity and high in computation efficiency.
Owner:ZHEJIANG UNIV OF TECH

Method for correcting track errors generated during iterative learning of industrial robot

A method for correcting track errors generated during iterative learning of an industrial robot comprises the following steps that firstly, a specific controlled object is determined, an electric current loop or a speed closed loop is adopted as the controlled object, and optimizing and setting of control parameters are carried out on a whole control loop; and secondly, according to the formula (please see the specification), the learning gain phi is changed, the position of the starting point of a N(z) Nyquist curve and the amplitude of the curve are adjusted, introduced offline lead compensation factors enable the N(z) Nyquist curve to achieve translation, more curves fall into a unit circle, gamma=1,2,3...n, and in the formula, q is the feedback gain, and gamma is the number of samplingperiods. According to the method, the design of a robot iterative learning controller is provided according to the characteristic that the industrial robot operates on the same track multiple times,the robot has the self correction capacity, the experience in the previous operating track process is gained to guide operating of subsequent tracks, the more the robot operates, the higher the accuracy is, following errors are reduced greatly, and the accuracy of track operating is improved.
Owner:重庆固高科技长江研究院有限公司

SIFT parallelization system and method based on recursion Gaussian filtering on CUDA platform

Provided are an STFT parallelization system and method based on recursion Gaussian filtering on a CUDA platform. The method comprises the steps that first, original images are transmitted to a GPU end for conducting a series of Gaussian filtering and downsampling to establish a Gaussian pyramid, Gaussian filtering is conducted through a recursion Gaussian filter, and then substraction is conducted on the adjacent images to obtain a Gaussian difference pyramid; second, a thread block is used as a unit to load in an image, each thread is used for processing one pixel, and the pixel is compared with the adjacent 26 pixels to obtain local extreme points; third, each thread is used for processing one local extreme point, and positioning and selecting of key points are conducted; fourth, one thread block is used for calculating the direction of one key point, one thread is used for calculating the direction and the amplitude value of one pixel in the neighbourhood of the key point, the direction and the amplitude valve are accumulated to a gradient histogram through an atomic addition provided by a CUDA, and the information such as the coordinates and the directions of the key points are transmitted to a host end according to the directions of the key points obtained by the gradient histogram; fifth, one thread block is used for calculating one key point descriptor, then a calculating result is transmitted to the host end, and SIFT feature extraction is achieved. The STFT parallelization system and method based on the recursion Gaussian filtering on the CUDA platform improve the calculating speed of an SIFT algorithm.
Owner:北京航空航天大学深圳研究院
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