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1791results about How to "Efficient construction" patented technology

Transformerless static voltage inverter for battery systems

A static inverter for a battery of elementary, current sources or cells electrically in series and a number N of intermediate voltage taps along the chain of elementary DC current sources, wherein the number of elementary cells comprised between an intermediate tap and another intermediate tap adjacent to it or an end terminal of said chain is proportionate to the amplitude in the respective phase interval of a number N of discretization phases of the waveform of the AC voltage to be output in a quadrant; is implemented by arranging for: a number N of power switches each connecting a respective intermediate tap and a first end terminal of a first polarity of said chain of elementary cells in series to a common circuit node of said first polarity; an output bridge stage constituted by at least four power switches controlled in pairs for switching the current paths through the bridge stage, having a first pair of nodes coupled to said common circuit node of said first plurality and to the other end terminal of polarity opposite to said first polarity of said chain of elementary cells, respectively, and a second pair of nodes constituting an AC output; and a control circuit sequentially and cyclically turning on, in a continuous manner, one switch at the time of said N switches; each for a phase interval of 1/(4N) times the period of said AC output, and alternately tuning on by pairs said four power switches of said output bridge stage at every half a period.
Owner:SQUIRREL HLDG

Hardware-efficient low density parity check code for digital communications

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes. Variations including parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.
Owner:TEXAS INSTR INC

Interactive automated testing system and method thereof

The invention discloses an interactive automated testing system and a method of the interactive automated testing system. The interactive automated testing system comprises a test master control end which is respectively connected with an automatic use-case editor and a plurality of agent actuating ends. The automatic use-case editor is connected with an interface record module through a recorded control library file. The automatic use-case editor and the test master control end are provided with a similar natural language manager. The interactive automated testing system and the method of the interactive automated testing system firstly solves the problem how to achieve generation and usage of temporary storage data variable, and how the interactive automated testing system achieves unified management of life cycles of the data variable when a traditional mode that a programming script drives an automated testing is abandoned so as to achieve high-speed generation of an automated testing use-case, and secondly solves the problems that how to automatically and accurately marking positions of occurrences of issues on a picture after the automated testing carries out an automatic screenshot, and how to accurately and detailedly scripting the problems, and meanwhile a issue script is printed on the picture and is used as issue remark of the picture.
Owner:彭勇

Soil pressure balancing type tunnel shielding simulation experiment system

The invention relates to a soil pressure balance type tunnel shield analog experiment system, a rectangular soil coelom with the upper part provided with an opening is internally provided with a shield machine model and filled with a simulated soil body, the axle wire of the shield machine model is overlapped with that of the soil coelom; the upper surface of the simulated soil body is covered with a layer of concrete cushion the upper surface of which is connected with a horizontal loading beam by more than two soil pressure jacks, the horizontal loading beam is connected with the bottom of the soil coelom by an anchor rope; and the simulated soil body is also internally embedded with a soil pressure box, a grating fiber optical sensor and a displacement meter, wherein, the soil pressure box, the grating fiber optical sensor and the displacement meter are all electrically connected with a data acquisition and processing device. The system can simulate the influence of shield tunnel construction between subways of cities on the stratum and surrounding environment more conveniently, actually and effectively, and provide more actual and accurate experimental data for tunnel construction and design so as to guarantee the high-efficiency and safety of the shield tunnel construction of cities.
Owner:SOUTHWEST JIAOTONG UNIV

Hardware-Efficient Low Density Parity Check Code for Digital Communications

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclosed. The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes. Variations including parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.
Owner:TEXAS INSTR INC

CRISPR/Cpf1 plant genome directional modification function unit, carrier comprising function unit, and application thereof

The invention belongs to the technical field of gene engineering, and concretely relates to a CRISPR/Cpf1 plant genome directional modification function unit, a carrier comprising the function unit, and application thereof. The invention aims to build an effective plant genome CRISPR/Cpf1 directional modification framework carrier according to an action principle of a CRISPR/Cpf1 system and a vegetable cell gene expression characteristic, and realize high-efficient application thereof in plant genome directional modification. The technical scheme provided by the invention is characterized by building the CRISPR/Cpf1 plant genome directional modification framework carrier formed by lachnospiraceae bacterium Cpf1 nuclease protein (LbCpf1) expression unit and a guiding crRNA transcription expression unit. The invention also provides a method for designing specificity-guided crRNA and building a CRISPR/Cpf1 recombinant expression vector aiming at rice genome target loci by adopting the CRISPR/Cpf1 plant genome directional modification framework carrier. The invention provides the high-efficient CRISPR/Cpf1 plant directional modification framework carrier, which can effectively realize simple, fast and high-efficient directional modification based on the CRISPR/Cpf1 system aiming at a plant genome target sequence.
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

Construction method and application of genome-wide methylation high-throughput sequencing library and

The invention provides a construction method and application of a genome-wide methylation high-throughput sequencing library. The construction method of the genome-wide methylation high-throughput sequencing library comprises steps of: conducting digestion on a genome DNA with Msp I and a second restriction endonuclease; conducting end repair on DNA fragments; adding a basic group A on a 3'terminal of the DNA fragment subjected to end repair; connecting a DNA fragment with a cohesive end A to a methylation joint; conducting fragment selection on the connect products with the methylation joint, in order to obtain a target fragment; subjecting the target fragment to a bisulfite treatment, in order to convert unmethylated cytosine in the target fragment to uracil; subjecting the converted target fragment to PCR amplification; and separating and purifying the amplification products, wherein the amplification products form the genome-wide methylation high-throughput sequencing library. The construction method and application of the genome-wide methylation high-throughput sequencing library provided by the invention can conveniently and effectively construct the genome-wide methylation high-throughput sequencing library of the genome DNA sample.
Owner:TIANJIN MEDICAL LAB BGI
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