356results about "Data merging" patented technology

A wireless communication device (300) and corresponding system therein uses a plurality of biometric sensors (206, 208, 210) for assessing the identity of a user requesting access to a feature or service provided via the wireless communication device (300). A method comprises collecting (410) a biometric sample from one of the sensors and enabling the feature or service (414) when the sample matches a known sample (412) corresponding to the user. Preferably a sensor will be selected, based on evaluating whether a corresponding predetermined condition exists (406), from a list of the plurality of sensors that is prioritized according to accuracy and ease of use of the sensor.

The present invention relates to methods and apparatus for establishing a precoding codebook for a Multiple Input Multiple Output (MIMO) wireless communication system. The precoding codebook includes a plurality of codebook entries. Each codebook entry includes four sets of vectors for four respective corresponding transmission ranks. The vectors may be predetermined, or generated from source unitary matrices. In addition, the codebook is fully nested.

An apparatus and method for inverting a 4×4 source matrix. A source matrix is divided into four 2×2 sub-matrices. A plurality of sub-matrix products are subsequently calculated from the sub-matrices. Next, a determinant of the source matrix is calculated to form a determinant residue utilizing the previously computed sub-matrix products. Calculation of partial inverse for each sub-matrix is next performed, using the sub-matrix products and determinants of the sub-matrices. Finally, an inverse of each sub-matrix is calculated, utilizing the partial inverse sub-matrices and the determinant residue to form an inverse of the 4×4 source matrix. The article allows processors to store two floating-point elements within a Single Instruction Multiple Data (SIMD) register. Accordingly, a sub-matrix is represented using two SIMD registers, resulting in improved computational locality and efficiency. Other embodiments are described and claimed.

Some embodiments of the invention provide configurable integrated circuit (IC) that includes several configurable circuits that are conceptually in tiles. The IC also includes a first data network for passing data between the configurable circuits. The IC further includes a second packet-switch network for receiving packets of data from the outside of the configurable IC and switchably routing each packet to at least one destination tile. In some embodiments, the second packet-switch network supplies data from the tiles that the configurable circuits output in response to data packets received from outside of the configurable IC. Also, in some embodiments, a particular packet that is for a particular resource in a particular tile includes a fist address that identifies the particular configurable tile from the plurality of configurable tiles, and then a second address that identifies the particular resource within the particular configurable tile.

A matrix processor and processing method, the processor including a data encoder for receiving an input data stream; a data controller coupled to the data encoder for arranging the input data in an operand matrix, at least one processing unit for processing the data in matrix form by Boolean matrix-matrix multiplication with a selected operator matrix, and an output control module coupled to the processing unit for outputting desired results therefrom.

Techniques for optimizing sparse matrix-vector multiplication (SpMV) on a graphics processing unit (GPU) are provided. The techniques include receiving a sparse matrix-vector multiplication, analyzing the sparse matrix-vector multiplication to identify one or more optimizations, wherein analyzing the sparse matrix-vector multiplication to identify one or more optimizations comprises analyzing a non-zero pattern for one or more optimizations and determining whether the sparse matrix-vector multiplication is to be reused across computation, optimizing the sparse matrix-vector multiplication, wherein optimizing the sparse matrix-vector multiplication comprises optimizing global memory access, optimizing shared memory access and exploiting reuse and parallelism, and outputting an optimized sparse matrix-vector multiplication.

A system and method for successively transposing a matrix is disclosed. The device includes a plurality of data storage elements arranged as a two dimensional (2D) structure including X rows and Y columns. The device further includes write control logic coupled to the input of plurality of data storage elements for writing data in at least one virtual row. The device also includes read control logic coupled to the output of the plurality of data storage elements for reading the data from at least one virtual column, where the data write to the at least one virtual row and the data read from the at least one virtual column are performed substantially simultaneously during each cycle of operation such that the 2D structure is transposed successively with zero cycle delay between successive transposes.

A plurality of log processes are synchronized. Each is independently performed in parallel with one another, into a single set of log files. A line buffering mechanism of an operating system (OS) of the computing environment forecloses interleaving of the log processes. Log management operations are concurrently performed by a single process protected by a file-system lock of the OS. The log management operations include at least one of a log compression, log retention, and log rotation operation.

A method for solving a matrix equation AX=B, wherein A represents a block sparse matrix, B represents a right hand side block vector and X represents a solution block vector. In one embodiment, the method includes receiving the block sparse matrix and the right hand side block vector, constructing a reduced transformed block sparse matrix from the block sparse matrix, constructing a reduced transformed residual block vector from the block sparse matrix and the right hand side block vector, and solving for the solution block vector using the reduced transformed block sparse matrix and the reduced transformed residual block vector.

A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.

Systems methods and recordable media for predicting multi-variable outcomes based on multi-variable inputs. Additionally, the models described can be used to predict the multi-variable inputs themselves, based on the multi-variable inputs, providing a smoothing function, acting as a noise filter. Both multi-variable inputs and multi-variable outputs may be simultaneously predicted, based upon the multi-variable inputs. The models find a critical subset of data points, or “tent poles” to optimally model all outcome variables simultaneously to leverage communalities among outcomes.

Generally, a method and apparatus are provided for computing a matrix inverse square root of a given positive-definite Hermitian matrix, K. The disclosed technique for computing an inverse square root of a matrix may be implemented, for example, by the noise whitener of a MIMO receiver. Conventional noise whitening algorithms whiten a non-white vector, X, by applying a matrix, Q, to X, such that the resulting vector, Y, equal to Q·X, is a white vector. Thus, the noise whitening algorithms attempt to identify a matrix, Q, that when multiplied by the non-white vector, will convert the vector to a white vector. The disclosed iterative algorithm determines the matrix, Q, given the covariance matrix, K. The disclosed matrix inverse square root determination process initially establishes an initial matrix, Q₀, by multiplying an identity matrix by a scalar value and then continues to iterate and compute another value of the matrix, Q_n+1, until a convergence threshold is satisfied. The disclosed iterative algorithm only requires multiplication and addition operations and allows incremental updates when the covariance matrix, K, changes.

A masking film has a unique polymeric binder in the imageable layer that enables the imaged film to be readily solubilized in non-chlorinated developers when it is used to form a relief image in a radiation-sensitive element, such as a UV-sensitive flexographic printing plate precursor. The polymeric binders in the imageable layer are resins that can be dissolved or dispersed in cyclohexane at 10% solids at 23° C. within 24 hours.

A privacy-preserving scalar product calculation system is provided. A first unit linearly transforms an n-dimensional vector Va into an n-dimensional vector based on a scalar value based on a random number W_i and a random number R_j to calculate a remainder by dividing each element of the linearly transformed n-dimensional vector by a random number M_i, and transmits an n-dimensional converted vector X including each of the remainders as its element to the second unit, the second unit calculates an inner product value Z based on the received n-dimensional converted vector X and an n-dimensional vector Vb, and transmits the inner product value Z to the first unit, and the first unit further calculates, based on a reciprocal of the scalar value and the receive inner product value, a scalar value and which calculates a remainder by dividing the scalar value by the random number M_i.

A system processes medical report data associated with different types of imaging modality devices to provide a composite examination report. An acquisition processor in the system acquires multi-modality medical imaging examination report data for examinations performed on a patient by different types of imaging modality device. A report processor processes acquired multi-modality medical imaging examination report data items by, in response to predetermined selection riles, selecting between individual data items in the acquired multi-modality medical imaging examination report data items to provide a single individual data item for incorporation in a composite report. The report processor maps individual data items including the single individual data item in the acquired multi-modality medical imaging examination report data items to corresponding data fields in a composite report data structure in memory in response to predetermined mapping information. An output processor outputs data representing the composite report to a destination device.

System and method for controlling/analyzing a process by solving a system of linear equations in real-time. Linear equations that model the process are stored. In an off-line stage a partitioning strategy is determined based on the linear equations, including determining groups of values for recursively partitioning a set of values measured and/or computed from the process. In an on-line stage: current process data are received from the process, including measurements from the process, and composing a set of values; the linear equations are recursively solved for a first group of the set, where the first group partitions the set into respective subsets of values, and where the recursively solving produces solved values for respective first groups of the set/subset of values; the linear equations are solved for remaining unsolved values in the set, thereby producing solved values for the set, which are stored and are useable to control/analyze the process.

A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented (290) that uses un-rolled pipelined CORDIC processors (245a to 245d) iteratively to improve throughput and resource utilization, while reducing the gate count.