112 results about "Short loop" patented technology

To alleviate the requirement to back-off all up-link performance, such as by limiting power spectral density, to overcome far-end cross-talk problems otherwise associated with relatively short loop-length wireline links, the present invention partitions the frequency spectrum based on an estimate of the loop length of a subscriber unit (CPE) modem from an exchange (LTE) modem. Up to a threshold frequency (fmax) at which received transmissions from a subscriber having a longest loop length (115) become indistinguishable by the LTE modem from a noise floor (102), up-link performance on all loop lengths is limited to correspond to that of the longest loop. At frequencies above the threshold frequency (fmax), subsets of subscribers (152-154) having relatively short loop lengths (116-119) use high frequency carriers that have signal to noise ratios sufficient to support information transmission in these elevated frequency bands.

When an instruction stored in a specific instruction buffer is the same as another instruction stored in another instruction buffer and logically subsequent to the instruction in the specific instruction buffer, a connection is made from the instruction buffer storing a logically and immediately preceding instruction, not the instruction in the other instruction buffer, to the specific instruction buffer without the instruction in the other instruction buffer, and a loop is generated by instruction buffers, thereby performing a short loop in an instruction buffer system capable of arbitrarily connecting a plurality of instruction buffers.

A method of adjusting focus and/or other image parameters in a remotely-operated image capturing system, such as a scanning electron microscope (SEM), is provided. The method minimizes transmission bandwidth and allows a remote user to perform adjustment quickly without requiring real-time feedback. In accordance with the method, rather than adjusting a knob or slider while viewing a real-time image as is done in prior art systems, the user selects among several still images representing a wide range of values of the adjustment in question. The user then selects from another set of images which represent a small subrange of values determined by the first choice. The process is repeated until the adjustment resolution of the instrument is reached or the user is satisfied. Adjustments, like objective lens alignment, which require “focus wobble” can also be made using this method. Since focus wobble is a periodic motion, it can be represented using a short loop of animation. This animation, when used in accordance with the present invention, can either be captured directly as a short burst of video or captured as a sequence of still images.

The invention relates to a method and device for constructing low-density parity check-code checking matrix. The constructing method is easy and flexible to implement, because the combination of semirandom constructing mode and structured constructing mode is adopted; besides, the arrays in the basis matrix are arranged in a special manner, the characteristics of irregular codes are achieved and the regularity is ensured. Therefore, the invention not only ensures excellent performance of low-density parity check-code, but also facilitates realization of coding hardware. In addition, short-loop is avoided in the basis matrix during the constructing process, and equal circular shift factors occur in the model matrix; thereby, the checking matrix has no short loop after expansion, and the decoding effect is improved. The invention also provides a group of selected model matrixes that can be expanded into multi-code length. The low-density parity check-code checking matrix with multi-code rate has an extensive application scope and excellent performance.

A return-on-investment (ROI) modeling system and method of the present invention calculates a return-on-investment for various scenarios in a semiconductor or data storage fabrication facility ("fab"). The ROI system and method of the present invention calculates the ROI based upon having fab operational details entered. The ROI calculation may be performed for an entire fab or a particular fab processing line. The present invention compares the ROI of a current operation with a contemplated change or set of changes. A complete set of pertinent factors having a relevant or significant impact on an accurate ROI calculation is taken into consideration. Further, the present invention determines costs associated with, for example, the installation of a new tool, downtime costs, short-loop test runs, split-lot testing, design-rule shrinks, and wafer-size changes. If a fab is not currently operating at maximum capacity, an embodiment of the invention calculates an increased capacity capability.

The invention discloses an algebraic construction method of LDPC (Low Density Parity Check) code based on cyclic matrixes; design parameters of cyclic matrixes are adjusted by short-loop check and minimum code weight check, which are nonnegative prime numbers a and b meeting two constraint conditions, and dimension q of an identity matrix, wherein the magnitude of dimension q of a shift identity matrix and whether the error rate characteristics of the designed LDPC code are influenced by prime numbers. The invention solves the problems of short-loop and low code coincident code word appearing in the existing QC LDPC code design. The method can check the existence of low code coincident code word in the designed code, thereby checking the existence of 4-loop. An irregular quasi-cyclic LDPC code structure disclosed by the invention divides the check matrix H into two submatrixes A and B, the nonsingular structure of the submatrix A is disclosed, and a matrix is generated by the two submatrixes A and B. Direct linear coding is carried out by generating the matrix. The embodiment validates the efficiency and good bit rate performance of the method disclosed by the invention.

A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.

A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.

The invention discloses a polarization code belief propagation decoding method based on a dynamic check matrix to solve the problems of the prior art that performance is low and time complexity is high when a traditional BP decoding algorithm is used. The method comprises the steps of 1, setting module parameters; 2, initializing parameters; 3, adjusting the check matrix to be in a low-density form; 4, executing belief propagation decoding; 5, judging whether a codon estimation vector is an effective vector; 6, calculating the minimum value of an absolute log likelihood; 7, calculating a threshold value; 8, judging whether decoding succeeds; 9, outputting a decoding result. By adjusting the polarization code check matrix and reducing the number of short loops of the check matrix, rapid convergence of the BP algorithm is achieved, and low time complexity is maintained while polarization code decoding performance is improved by means of the early-stage stop standard.

Methods, apparatuses, and processors for packing multiple iterations of a loop in a loop buffer. A loop candidate that meets the criteria for buffering is detected in the instruction stream being executed by a processor. When the loop is being written to the loop buffer and the end of the loop is detected, another iteration of the loop is written to the loop buffer if the loop buffer is not yet halfway full. In this way, short loops are written to the loop buffer multiple times to maximize the instruction operations per cycle throughput out of the loop buffer when the processor is in loop buffer mode.

A delay mismatched feed forward power amplifier is disclosed. Loop 1 includes a main amplifier and is used to derive a carrier cancelled sample of the main amplifier output. Loop 2 includes an error amplifier used to amplify the carrier cancelled signal derived from Loop 1 operation in order to cancel distortion products generated due to the nonlinear nature of the main amplifier. Loop 2 also utilizes a very short Loop 2 delay line. A significant efficiency gain is provided due to reduced output power losses associated with the Loop 2 delay line. Lower output losses also results in lower distortion levels produced by the main amplifier. This, in turn, reduces the size and performance requirements placed on the error amplifier. A smaller and more efficient error amplifier is employed resulting in further amplifier system efficiency improvement. The delay mismatch is compensated by a third control loop, a special adaptive control algorithm or a combination thereof.

A netting, knitted from fringes and weft threads is provided in which at least one fringe in at least one marginal region of the netting is shorter than the remaining fringes of the netting. The invention relates, furthermore, to a method for producing the netting on a knitting machine, during the knitting of the netting shorter loops for forming stitches from which the fringes are knitted being generated in at least one marginal region than in the remaining regions of the netting. Moreover, a knitting machine for producing a netting is described, which comprises a first lay bar for feeding the weft threads, a second lay bar for feeding the longitudinal threads, a needle bar with needles and a take-up device, at at least one position on the needle bar at which the marginal region of the netting is knitted the needle being positioned higher than the remaining needles.

A method and apparatus for testing the proper operation of an electronic pet containment transmitter. The transmitter includes an internal short loop antenna that is used to activate the receiver unit when it is brought into close proximity of the transmitter.

This invention provides a fan system connected to a supply provider and receiving a supply generated by the provider composed of an energy storage device, a motor, a drive device and a start up device, in which, the energy storage device receives and stores said supply, said motor is connected with said energy storage device and receives said supply, said drive device is connected between the energy storage device and the motor to form a control path, said start up device is connected between the energy storage device and said motor to form a supply path. When said fan system does not receive the supply of said provider, said storage device will release the stored supply, and said start up device generates an initiating signal to said motor to form a short loop to brake.

The invention discloses a Dewar with magnetic shielding or electromagnetic shielding. The Dewar is composed of an inner barrel and an outer barrel, wherein the two closed barrels are in sleeve joint; and the space between the inner barrel and the outer barrel is vacuumized, and a group of magnetic shielding bodies or electromagnetic shielding bodies are arranged between the inner barrel and the outer magnetic field of Dewar. Each magnetic shielding body is made into a strip shape or sheet shape by the use of a silicon steel sheet, or is integrally formed by the use of an outer barrel wall made from magnetic-conduction stainless steel; the electromagnetic shielding body can adopt coils formed by winding conductive material; and the coils are closed end to end to form a short loop surrounding the main magnetic field, or metal plates are welded to form a closed barrel shape. Through the invention, adverse impacts of the outer magnetic field on a superconducting magnet can be shielded or reduced at the same time.

By allowing the block rate to vary, the existing Asymmetric Digital Subscriber Line (ADSL) system is modified to better address extended reach and higher data rates. A method is disclosed for providing improved reach from the ADSL standard by reducing the block rate from the ADSL standard and providing improved data rate for short loops by increasing the block rate from the ADSL standard.

The present invention belongs to the technical field of channel coding and relates to a method for generating an RC-LDPC code check matrix. The method is based on the complexity of the coding, and is modified based on the PEG algorithm to construct a check matrix with a lower triangular form. The obtained coding complexity is linear. On this basis, the method of expanding the check bit step by step is adopted to support the flexible and variable code rate, which provides a feasible channel coding method for the adaptation of a wireless link. At the same time, the obtained series of sub-codes also have a lower triangular form, which almost does not increase the complexity but can achieve linear coding with regard to the mother code. According to the invention, the method utilizes the PEG algorithm to optimize the position of the nonzero element in the expanded part and optimizes the code structure so as to eliminate the short loop, to reduce the computational complexity of the codec and to further improve the transmission performance.