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133 results about "Loop length" patented technology

Low density check code check matrix constructing method based on shift matrix classified extension

A method for LDPC check matrix configuration based on circular shift matrix grading extension, which comprises configuring a master matrix exclusive of loops with the length of 4, then searching the distribution of loop 6, 8 and 10 in the master matrix, adopting grading expansion method to fill the displacement parameters of the circular shift matrix in the position of 1 element in the master matrix, and finally using circular shift matrix and all 0 matrix to fill the master matrix expansion according to the positions of displacement parameter matrix and 0 element so as to generate check matrix. For timely and effective discovery of good codes with secondarily maximized minimum loop length and average minimum loop length, the invention only requires graded optimization of the combination of the master matrix with very small code length and the circular shift matrix; compared with the method of random circular shift configuration check matrix followed by comparing average minimum loop length, the search volume is significantly reduced. The check matrix not only has excellent performance, but also further reduces average iteration times. The invention is suitable for all methods that adopt circular shift matrix to constitute check matrix.
Owner:PLA UNIV OF SCI & TECH

Integrated circuit package having an inductance loop formed from a multi-loop configuration

An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.
Owner:GCT SEMICONDUCTOR INC

Low density parity check (LDPC) code check matrix construction method and corresponding matrix multiply operation device

The invention relates to a low density parity check (LDPC) code check matrix construction method and a corresponding matrix multiply operation device. The method comprises the following steps that: determining the length n*L of a code word, the size L of a circulating replacement sub-matrix, a code rate L and number of rows m*L of a check matrix, wherein the size Hb of a basic matrix is m*n, the size H of the check matrix is mL*nL; determining best distribution of the check matrix H; constructing a basic matrix Hb with maximal loop length; exapdning the obtain basic matrix Hb to a quasi-cyclic-low density parity check (QC-LDCP) code with the loop length being maximized by selecting an appropriate movement factor, and determining the entire check matrix H by selecting the movement factor with element of a 1 position in the basic matrix Hb. The device comprises a check parity generating unit, an information sequence generating unit, a segmenting unit and a multiply unit. Due to the adoption of the method and the device, the coding complexity is reduced, the LDPC code with an error check performance being very approximate to a random structure is obtained, and simultaneously the realization complexity of the LDPC code is reduced.
Owner:上海新微科技发展有限公司

Network and method for clock synchronization of clusters in a time triggered network

The invention relates to a network operating on a time triggered protocol using time slots, wherein at least two clusters are included in the network, each cluster includes at least a node. Further, it relates to a method for clock synchronization within a time triggered network. To provide a network and a method reducing the amount of time needed for aligning multiple communication clusters as much as possible it is proposed to provide a network operating on a time triggered protocol using time slots, wherein at least two clusters (A, B, X) are included in the network, each cluster (A, B, X) includes at least a node (11), wherein the node (11) includes a communication controller (15) having a node clock source (18) for determining a timing for the node (11), wherein the clusters (A, B, X) are connected to a coupling unit (10) having a clock alignment control logic (20) comprising a coupling unit clock source (21) which is more accurate than the node clock source (18), wherein the coupling unit clock source (21) is used for aligning the timing between the at least two clusters (A, B, X). Further it is proposed to provide a method for clock synchronization within a time triggered network using time slots, having at least two clusters (A, B, X), wherein each cluster includes at least one node (11), each node (11) comprises a node clock source (18) and a communication controller (15) and the clusters (A, B, X) are connected to a coupling unit (10) having a clock alignment control logic (20) comprising a coupling unit clock source (21) which is more accurate than the node clock source (18), the method comprising the steps of: monitoring the timing of the connected clusters (A, B, X) within the coupling unit (10); increasing or decreasing a cycle length of the timing within the clusters by use of the coupling unit clock source (21).
Owner:NXP BV

Method for automatically improving per-second flow balance of strip steel in hot continuous rolling strip threading process

ActiveCN104801548AIntelligent adjustment of speed ratioAdapt to changes in external working conditionsFlexible work arrangmentsMass flow control deviceLoop lengthEngineering
The invention provides a method for automatically improving per-second flow balance of strip steel in the hot continuous rolling strip threading process. Due to the fact that 'later' intervention of an operator is basically correct, the per-second flow balance can be changed more reasonable, an ideal rack speed matching value of a piece of steel is calculated by analysis the loop length and manual invention amount of the operator in the strip threading process and used for correcting setting of a next piece of same-specification steel. Compared with routine techniques, the method is characterized in that 'later intervention' is converted into accurate 'advanced correction', accordingly a complicated and tedious forward slip formula is omitted, and racks can have an 'intelligent learning' function on the speed aspect. According to the method, the complicated and tedious forward slip formula is omitted, and a method for automatically adjusting per-second flow matching between racks is found. The method is used for improving the per-second flow balance in the hot continuous rolling strip threading process and improving rolling stability so as to decrease strip steel head rolling breakage times and width decrease times. In addition, automation degree of strip threading is improved, and the working load of the operator is decreased.
Owner:BAOSHAN IRON & STEEL CO LTD
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