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Short-loop-free QC-LDPC code rapid generation method

A short-loop and fast technology, applied in coding, code conversion, coding components, etc., can solve problems affecting coordination efficiency, decoding speed and success rate, affecting system security code rate and transmission distance, etc.

Active Publication Date: 2020-01-31
NO 30 INST OF CHINA ELECTRONIC TECH GRP CORP
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Problems solved by technology

[0006] In order to overcome the above-mentioned shortcomings of the prior art, the present invention provides a fast generation method of QC-LDPC codes without short loops, aiming to solve the problem that the LDPC code parity check matrix affects coordination due to short loops in actual CV-QKD system applications. Efficiency, decoding speed and success rate, which in turn affect the security code rate and transmission distance of the system

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Embodiment Construction

[0019] A fast generation method for QC-LDPC codes without short loops for QKD systems, the implementation steps are as follows figure 1 As shown, this method is suitable for the problem that there is a short loop in the QC-LDPC code, which leads to the degradation of error correction decoding performance. The method of re-random assignment to select the cyclic shift amount of the acyclic state of the base matrix is ​​used to construct the checksum of the QC-LDPC code. matrix.

[0020] For polygonal LDPC codes, each type of edge represents a sub-matrix, and the process of generating the matrix is ​​(taking three types of edges as an example):

[0021] Step 1: Generate sub-matrices H1, H2, and H3 of various edges according to the degree distribution function and the compression factor Q, and randomly assign the cyclic shift amount of each edge 1 to Q.

[0022] First, the compression factor Q and the code length need to be determined. Since the size of the generated parity chec...

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Abstract

The invention discloses a short-loop-free QC-LDPC code rapid generation method, which comprises the following steps: step 1, generating sub-matrixes of various edges according to a degree distributionfunction and a compression factor Q, and randomly assigning cyclic shift amounts of each edge 1-Q; step 2, arranging the sub-matrixes according to the positions of various edges to construct a basismatrix; step 3, traversing each node of the sub-matrix to search for a short ring, and randomly assigning 1-Q cyclic shift values again to eliminate the short ring; and step 4, expanding the basis matrix into a check matrix according to the cyclic shift amount of each edge. Aimed at problems in an actual QKD system, the coordination efficiency, the decoding speed and the success rate of an LDPC code check matrix are influenced due to the existence of a short loop, and then the safety code rate and the transmission distance of a system are influenced, the invention provides the short-loop-freeQC-LDPC code quick generation method suitable for the QKD system. The short-loop-free check matrix can be quickly generated, and the decoding performance is improved.

Description

technical field [0001] The invention relates to a method for quickly generating short-cycle QC-LDPC codes used in a QKD system. Background technique [0002] In 1962, Gallager proposed Low-Density Parity-Check codes (Low-Density Parity-Checkcodes, LDPC) for the first time. LDPC codes have been widely studied because of their high performance close to the Shannon limit. At the same time, LDPC codes are easy to implement in parallel, so many standards use LDPC codes as channel coding schemes. In recent years, Quasi-Cyclic Low-Density Parity-Check codes (Quasi-Cyclic Low-Density Parity-Check codes, QC-LDPC) have appeared. QC-LDPC codes are a very important class of LDPC codes, which can be implemented in the form of shift registers. Encoding greatly reduces the complexity of encoding and enables efficient encoding. [0003] At the same time, the LDPC code can be represented by a binary check matrix H, the number of 1 elements in each row and column of the matrix is ​​fixed, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/116
Inventor 马荔徐兵杰李扬杨杰黄伟
Owner NO 30 INST OF CHINA ELECTRONIC TECH GRP CORP
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