Constant-temperature instruction level self-testing method for testing time delay faults in inner heating manner

Abstract

The invention relates to a constant-temperature instruction level self-testing method for testing time delay faults in an inner heating manner. A processor is subjected to high-temperature time delay. The method comprises steps as follows: an original instruction level self-testing program module is obtained; the original instruction level self-testing program module is subjected to loop unrolling deformation; the original instruction level self-testing program module is subjected to deformation on basis of cache miss; feasible scheduling is acquired in a set test temperature interval with a constant-temperature test program scheduling algorithm; the processor is heated to the lower bound of the test temperature interval, corresponding programs are executed according to feasible scheduling, and inner heating type constant-temperature tests are performed aiming at the time delay faults. Compared with the prior art, the constant-temperature instruction level self-testing method has the advantages that the time delay faults can be tested effectively under a high-temperature condition, a high fault covering rate is guaranteed, and the loss of the processor is reduced, and the like.

Description

technical field [0001] The invention relates to the technical field of semiconductor technology, in particular to a constant-temperature command-level self-test method for detecting time-delay faults in an internal temperature-rising manner, and is a detection method for time-delay faults under high-temperature conditions of VLSI fault tolerance. Background technique [0002] High temperature has always been one of the key factors affecting the reliability of computer systems. Computer systems work correctly at normal operating temperatures. However, once the temperature rises, there will be a large number of incomprehensible failures in the computer system. This problem is prevalent even when the entire system of chips has undergone rigorous manufacturing testing. This temperature-related problem is mainly derived from the worst-case delay failure, that is, the delay failure under high temperature conditions. As the temperature of the chip increases, the delay of signal ...

AI Technical Summary

Problems solved by technology

Previous instruction-level self-test methods only considered low power consumption or low temperature to reduce test overhead

However, no work has considered an instruction-level self-test approach to detect time-delay faults at elevated temperatures

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