A fixed-temperature command-level self-test method for detecting time-delay faults by internal temperature rise

Abstract

The invention relates to a fixed-temperature command-level self-test method for detecting time-delay faults in an internal temperature rise mode. The high-temperature time-delay test is performed on a processor, comprising the following steps: obtaining the original command-level self-test program module; and performing the original command-level self-test program module Carry out the deformation of loop unrolling; carry out the deformation of the original instruction level self-test program module based on triggering cache miss; within the set test temperature range, use the fixed temperature test program scheduling algorithm to obtain feasible scheduling; heat the processor to the test temperature range The lower bound of , according to the feasible schedule, execute the corresponding program, and implement the constant temperature test of internal heating for delay faults. Compared with the prior art, the invention has the advantages of being able to effectively test delay faults under high temperature conditions, ensuring high fault coverage, reducing processor loss and the like.

Description

technical field [0001] The invention relates to the technical field of semiconductor technology, in particular to a constant-temperature command-level self-test method for detecting time-delay faults in an internal temperature-rising manner, and is a detection method for time-delay faults under high-temperature conditions of VLSI fault tolerance. Background technique [0002] High temperature has always been one of the key factors affecting the reliability of computer systems. Computer systems work correctly at normal operating temperatures. However, once the temperature rises, there will be a large number of incomprehensible failures in the computer system. This problem is prevalent even when the entire system of chips has undergone rigorous manufacturing testing. This temperature-related problem is mainly derived from the worst-case delay failure, that is, the delay failure under high temperature conditions. As the temperature of the chip increases, the delay of signal ...

AI Technical Summary

Problems solved by technology

Previous instruction-level self-test methods only considered low power consumption or low temperature to reduce test overhead

However, no work has considered an instruction-level self-test approach to detect time-delay faults at elevated temperatures

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