201 results about "Manufacturing testing" patented technology

A test sensor is made that is adapted to assist in determining the concentration of an analyte in a fluid sample. The method includes providing a lid and providing a base. The lid is attached to the base to form an attached lid-base structure. The lid-base structure has a first end adapted to receive the fluid sample and a second opposing end adapted to be placed into a meter. Auto-calibration information is assigned to the lid-base structure. The second opposing end is formed such that the shape of the second opposing end corresponds to the auto-calibration information.

A method is disclosed for configuring a data storage device. The data storage device receives a configuration code, and in response to the configuration code selects a configuration data record set from a plurality of configuration data record sets. The data storage device is configured in response to the selected configuration data record set. For example, the data storage device may be configured into a manufacturing test procedure mode, and then into a customer specific operating mode. In another embodiment, a hardware configuration of the data storage device is identified, and the configuration code selected based on the identified hardware configuration.

A test strip for determining the concentration of an analyte in a body fluid includes a membrane in fluid communication with a porous layer. The membrane and the porous layer are divided into compressed portions, which restrict the capillary flow of the body fluid, and uncompressed portions. The uncompressed portions are adapted to absorb and retain body fluids in excess of the amount required for operation of the test strip. The test strip may be constructed with an internal relief chamber to accommodate the uncompressed portions. A method of making the test strip by pressure and / or heat sealing individual components on a shaping die is also provided.

The present invention provides an electrochemical biosensor test strip used for quantitative determination of an analyte in a liquid sample. Methods of fabricating the test strip and reagent formulas are also provided. Improvements in electrochemical test strips are required to detect the presence of a compound in a liquid mixture using a smaller sample size with increased accuracy. The present invention was developed to be user-friendly, decrease sample requirements and decrease analyzing time while increasing the reproducibility and accuracy of the electrochemical test strip.

A structure and method for an integrated circuit which includes read / write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read / write memory; a comparator operative to compare retrieved data read from the read / write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read / write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.

An integrated circuit (IC) device fabrication process may be monitored by processing product wafers to fabricate product IC devices, collecting process tool data from tools used to fabricate the product IC devices, and testing the product IC devices. To predict and monitor yield, the process tool data collected during processing and the defectivity data from testing the product IC devices may be input to a yield model that also takes into account design information particular to the product devices. The design information may comprise layout attributes of the product devices. The yield model may be generated from a defectivity model created by processing test wafers to fabricate test structures, collecting process tool data from tools used to fabricate the test structures, and testing the test structures. The test structures may have varying layout attributes to cover a design space allowed by design rules for particular product IC devices.

A disk drive with switchable power levels for the heaters in the sliders is disclosed. The invention includes a switch for the electrical circuit of each heater which selects between two or more voltages to apply to the power control element and the heater with at least a high and a low voltage option. The heater power control circuit dissipates a certain amount of heat as a part of the control process. By having a low voltage option the disk drive can save power and reduce the amount of heat dissipated by the heater control circuit when high power is not required. The programmable switch is controlled by the drive control system. The high power setting can be used during manufacturing testing or otherwise if higher heater power is needed. The low power setting is used for normal operation or to save power.

Scan chains to support debugging and manufacturing test modes for integrated circuit chips are made adaptable. Scan chains may be configured either in a multiple scan chain JTAG mode or in a multiple independent and parallel scan chain mode. The configuration transition between the scan modes is made by private instructions implemented in a JTAG controller, which supports the IEEE 1149.1 standard.

A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

A process of manufacturing test strips of the type comprising a length of porous carrier material capable of acting as a liquid flow path for a sample liquid and having at least zone downstream from a first end of the strip which zone contains an immobilized specific binding agent to act as a capture means during an assay to reveal the presence of an analyte in applied sample liquid, and in which process the specific binding agent is deposited onto a sheet of the porous carrier material which is then blocked and subdivided into a plurality of individual identical test strips, wherein blocking of the porous carrier material is achieved by applying a solution of blocking agent to the sheet upstream from the zone in an amount sufficient to ensure that the solution permeates downstream to beyond the zone. Preferably there is a plurality of zones of immobilized agent arranged in series on the strip, and wherein blocking is achieved by applying a solution of blocking agent to the sheet upstream from the first of the plurality of zones in an amount sufficient to ensure that the solution permeats downstream to beyond the last of the plurality of zones.

An integrated circuit is provided with latency detecting circuitry for detecting signal generation latency within one or more functional circuits and in response thereto to generate a wearout response. The wearout response can take a variety of different forms such as reducing the operating frequency, increasing the operating voltage, operating task allocation within a multiprocessor system, manufacturing test binning and other wearout responses.

A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained from the nonvolatile memory, and used in applying an operating parameter of the communication channel. After applying the operating parameter, communication is initiated on a communication channel. The operating parameter can be adjusted to account for drift immediately after starting up, or periodically. The process of starting operation in the field includes power up events after a power management operation. In embodiments where one component includes memory, steps can be taken prior to a power management operation using the communication channel, such as transferring calibration patterns to be used in calibration procedures.

A manufacturing process for storing measured light output internal to an individual LED assembly, and an LED assembly realized by the process. The process utilizes a manufacturing test system to hold an LED light assembly a controlled distance and angle from the spectral output measurement tool. Spectral coordinates, forward voltage, and environmental measurements for the as manufactured assembly are measured for each base color LED. The measurements are recorded to a storage device internal to the LED assembly. Those stored measurements can then be utilized in usage of the LED assembly to provide accurate and precise control of the light output by the LED assembly.

A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and / or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and / or also to update supply chain forecasts.

The present invention provides novel osmium-based electrochemical species for the detection of wide variety of analytes using immunological techniques. The present invention also provides diagnostic kits and test sensors supporting electrode structures that can be used with the osmium-based electrochemical species. The test sensor can be fabricated to support interdigitated arrays of electrodes that have been designed to provide amplification of the electrical signal amplification desired to analyze analytes that may be present at low concentrations.

End of line effect can occur during manufacture of components using a lithographic apparatus. These end of line effects can result in line end shortening of the features being manufactured. Such line end shortening may have an adverse impact on the component being manufactured. It is therefore desirable to predict and / or monitor the line end shortening. A test pattern is provided that has two separate areas such that, as designed, when the two areas are illuminated with radiation (for example from an angle-resolved scatterometer) they result in diffused radiation with asymmetry that is equal in sign to each other, but opposite in magnitude. When the test pattern is actually manufactured, line end shortening occurs, and so the asymmetry of the two areas are not equal and opposite. From the measured asymmetry of the manufactured test pattern, the amount of line end shortening that has occurred can be estimated.

A method of identifying faulty programmable interconnect resources of a field programmable gate array (FPGA) may be carried out during manufacturing testing and / or during normal on-line operation. The FPGA resources are configured into a working area and a self-testing area. The working area maintains normal operation of the FPGA throughout on-line testing. Within the self-testing area, programmable interconnect resources of the FPGA are grouped and comparatively tested for faults. Upon the detection of one or more faults within a group of programmable interconnect resources, the group of resources is subdivided for further comparative testing in order to minimize a region of the group of resources including the fault for each fault. Once the region of the group of resources which includes the fault is minimized, the wires within the minimized region are comparatively tested in order to determine which wire includes the faulty resource or resources. Once the wire which includes the faulty resource is determined, a variety of testing configurations may be utilized to identify the faulty resource within the wire.

A method of making a test sensor configured to assist in determining information related to an analyte in a fluid sample is disclosed. The method comprises the act of providing a base having a first end and a second opposing end. The method further comprises the act of providing a fluid-receiving area configured to receive a fluid sample. The method further comprises the act of assigning calibration information to the test sensor. The method further comprises the act of forming at least one notch such that a depth of the notch corresponds to the calibration information.

A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

An R.F. transmitter circuit has an amplifier (30), a matching network (40) coupled to an output of the amplifier, a programmable resistance (35) coupled to the output of the amplifier, and a controller (60) arranged to control the programmable resistance, and to determine a matched output impedance of the amplifier by detecting a change in the amplifier output for different values of the programmable resistance. This output impedance can be used to adjust the matching to achieve optimum gain or optimum efficiency or other characteristic, during manufacture, test, or in use.

The invention relates to a high-alloy centrifugal compounding steelcasting support roll and a processing technique thereof. The high-alloy centrifugal compounding steelcasting support roll comprises the following chemical substances: a working layer containing 0.4-0.5 of C, 0.3-0.6 of Si, 0.4-0.8 of Mn, less than or equal to 0.035 of P, less than or equal to 0.03 of S, 3.5-4.5 of Cr, 0.2-1.0 of Ni and 0.2-0.5 of Mo, and the balance steel and impurities by weight; a core part containing 3.0-3.6 of C, 1.7-2.7 of Si, 0.2-1.0 of Mn, less than or equal to 0.08 of P, less than or equal to 0.01 of S, 0.01-0.04 of Re, 0.03-0.08 of Mg, less than or equal to 1.0 of Cr, less than or equal to 1.0 of Ni, less than or equal to 1.0of Mo, less than or equal to 1.0 of Cu, less than or equal to1.0 of V, and the balance iron and impurities by weight. Furthermore, the working layer is formed by horizontal type centrifugal pouring, the core part is formed by pouring, and the heat treatment is carried out in such a way that a trolley type high-temperature resistance furnace to heat a rough machining support roll in an austenite way and preserve the heat of the rough machining support roll. The invention has high abrasion resistance, high accident prevention and high working production ratio.