83results about "Integrated circuit testing" patented technology

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

The invention provides an integrated circuit performance testing method based on multi-dimensional parameter fusion, and belongs to the technical field of integrated circuit performance testing. S2, collecting multi-dimensional parameters; s3, data preprocessing; s4, carrying out multi-dimensional parameter fusion; and S5, performance test analysis. Through multi-parameter coverage, multi-algorithm collaboration and full-process closed loop, the problems of isolation, fragmentation and simplification of traditional testing are solved, and systematic and refined technical support is provided for performance testing of the integrated circuit.

The present disclosure provides a testing apparatus, which includes a plurality of devices under test (DUTs) and an advanced process control monitor (APCM). The APCM includes a switch circuit, a control circuit, a detection circuit, and an auxiliary control circuit. The switch circuit includes a plurality of switch devices corresponding to the DUTs. The control circuit includes a plurality of control devices corresponding to the switch devices, and is configured to sequentially activate one of the switch devices during a test procedure of the testing apparatus. The detection circuit is configured to provide a first power supply voltage to a first terminal of each switch device. The auxiliary control circuit is configured to provide a second power supply voltage to a second terminal of each switch device deactivated the control circuit.

The invention discloses an ASIC special password intelligent chip aging prediction method, and relates to the field of chip aging prediction, and the method comprises the steps: carrying out the feature fusion coding through obtaining chip power supply wiring layer data and collecting environment parameters, obtaining an aging sensitivity feature vector, carrying out the fractional order aging dynamics modeling based on the aging sensitivity feature vector, and carrying out the aging prediction. Performing chip aging state prediction based on the chip aging state change equation to obtain an aging track prediction sequence, extracting an aging sensitivity feature vector component and the aging track prediction sequence to perform residual life probability evaluation, and obtaining a residual life cumulative distribution function; on the basis of the residual life cumulative distribution function, uncertainty analysis is carried out on chip aging prediction to obtain a two-factor risk index, a coupling aging rule between hardware structure weakness and environmental stress is grasped, real aging sensitive points of the chip can be accurately reflected, and accurate reference can be provided for preventive maintenance of the chip.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

The invention provides a test method for testing a semiconductor device, which comprises the following steps of: executing at least one test item in a group of test items on the semiconductor device under a first environment condition; generating, by the machine learning model, an identification result based on the test results of the at least one test item, the identification result predicting at least one test result of performing one or more test items of the set of test items on the semiconductor device under a second environmental condition; and determining whether to perform one or more test items in the set of test items on the semiconductor device under a second environmental condition based on the identification result. According to the invention, based on the test result under the first environment condition, the machine learning model is utilized to predict and obtain the corresponding identification result, so that whether the test needs to be executed again under the second environment or not is determined according to the identification result.

The invention discloses a software ecological management method of automatic test equipment and application thereof, and belongs to the technical field of integrated circuit test. The method comprises the following steps: automatically writing a version identifier containing firmware information of an upper computer and a lower computer when a test program is compiled; when the program is loaded, the system obtains the actual version of the current operating environment and compares the actual version with the version identifier; if the versions are not matched, the system interrupts program execution through consistency verification and an interlocking controller, and a version switching manager is started; and the version switching manager automatically closes the current environment according to the version identifier, searches a version information base, switches the software of the upper computer, synchronously updates the firmware of the lower computer to a target version, and restores the test after the environment verification is passed. Through binding during compiling and forced verification during loading, automatic and accurate switching of the test environment is achieved, the problems that manual switching is prone to errors and software and hardware collaboration is poor are solved, and the test risk and the maintenance cost are remarkably reduced.

The invention discloses a test machine detection system and method, a medium and computer equipment, and belongs to the field of semiconductor tests.The method comprises the steps that a program detection code is run through a test machine; sending an instruction code to the detection board by using the test mother board; executing the instruction code by using the detection board; the detection result of the instruction code executed by the detection board is displayed by using the on-off of the light-emitting diode; a detection result is fed back to the test machine through the detection plate; performing data comparison on the detection result by utilizing the test machine, and if the detection result is abnormal, displaying fail output by utilizing a test interface; and if the detection result is normal, displaying pass output by using a test interface. According to the application of the invention, each module in the system can be detected, the detection result can be synchronously displayed on the test machine and the detection board, the abnormal position and the abnormal type of the abnormal module can be rapidly locked, and the formation of a rapid abnormal processing scheme is facilitated.

The invention relates to an intelligent chip aging test system and method. According to the system disclosed by the invention, high-precision dynamic monitoring and intelligent management of a plurality of aging chips are realized through integrated power supply management, multi-channel signal acquisition, redundancy control and remote communication. The system core comprises a power supply module, a signal acquisition module, a core processing unit and a plurality of peripheral equipment interfaces; according to the method, through staged power-on time sequence control, dual redundancy check, dynamic load simulation and cloud data synchronization, the test reliability and efficiency are remarkably improved, the method is suitable for high-temperature aging screening and quality evaluation of semiconductor devices, the production cost is effectively reduced, and production process optimization is supported. The invention belongs to the technical field of electronic testing.

To provide a technique that can improve accuracy of movement correction in a stage of moving relative to a probe card.SOLUTION: An inspection device perform electrical inspection of a substrate. The inspection device includes a probe card having a plurality of probes, a stage on which the substrate is placed, the substrate is moved relative to the probe card, and the substrate is brought into contact with the plurality of probes, and a control unit that controls the movement of the stage. The control unit uses a first displacement amount based on a vertical load of the probe card and a second displacement amount based on an unbalanced load of the probe card tilted with respect to the vertical load to calculate a three-dimensional correction amount in the unbalanced load and move the stage on the basis of the calculated correction amount.SELECTED DRAWING: Figure 4

The application provides a verification method and system of a maximum likelihood sequence detection chip, the verification method comprises creating a random environment, and a random model is created in the random environment; a verification environment is created, a reference model is run in the verification environment, and a device to be tested is run in the verification environment; the random environment is run, random configuration information is generated from the random environment and is sent to the reference model; the reference model forms a test signal according to the received configuration information, and inputs the test signal to the device to be tested; the reference model generates reference data according to the configuration information and outputs the reference data to a checker, the device to be tested generates running data after running according to the test signal and outputs the running data to the checker, and the checker compares the reference data with the running data and generates a verification result. The application also provides a verification system for realizing the above method. The application can realize decoupling of generation of configuration information and the verification environment, and improves the accuracy of chip verification.

A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

There is provided a test apparatus including a first power source which outputs a first voltage of predetermined magnitude or a first current of predetermined magnitude; a first switch unit which connects, to the first power source, a connection terminal of a device under test serving as a test target, among connection terminals of a plurality of devices under test; a first measuring unit which measures an electrical characteristic of the device under test serving as the test target in response to the first power source being connected to the device under test serving as the test target; and a second voltage source which outputs a second voltage of predetermined magnitude to a connection terminal of another at least one device under test which is different from the device under test serving as the test target, among the plurality of devices under test.

The application relates to the technical field of SRAM storage and calculation anti-radiation test, and discloses an SRAM storage and calculation anti-radiation test method and system based on running state injection, which comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; model quantization compilation, sensitivity analysis and physical bit candidate generation; running state injection plan generation and test case loading; running state execution, disturbance injection and synchronous monitoring collection; multi-source triggering, weight reading back and fault decoupling decision; anti-radiation performance quantitative evaluation, degradation curve construction and report output. The system and the method correspond to each other. The application constructs a hardware-in-the-loop running state injection and online evaluation technology, and realizes the technical problems of a guided disturbance / equivalent radiation injection based on weight bit level sensitivity and logic-physical mapping.

The invention relates to the technical field of chip failure analysis, in particular to a chip failure analysis path hierarchical decision and intelligent management and control method, which comprises the following steps: determining whether to perform data optimization or not according to a path abnormal frequency ratio of a target analysis model to obtain an optimized target analysis model; in the data optimization, a supplementary strategy of associated data supplementation is adopted, and whether the supplementary strategy comprises failure analysis supplementation or not is determined according to the high-frequency associated abnormal chip data proportion; in the failure analysis supplement, an outlier parameter is directly determined according to a related reference value or whether the outlier parameter is an outlier parameter or not is secondarily determined according to a deviation reproduction frequency ratio and a parameter emergence coefficient, data supplement is carried out for each outlier parameter, and whether global disturbance analysis supplement is carried out or not is determined according to a global abnormal coefficient. The analysis efficiency and the result reliability can be improved.

A system for testing a sensor and a hub is provided. The system includes a testing control device and a sensor testing device. The testing control device is configured to select a testing profile based at least in part on the sensor, and transmit a testing initiation signal based at least in part on the testing profile. The sensor testing device is configured to perform testing of the sensor and the hub in response to the testing initiation signal, the testing including rotating the sensor along at least one axis based at least in part on the testing profile, and transmit test data to the testing control device based at least in part on the testing of the sensor and the hub. The testing control device is configured to receive the test data from the sensor testing device.

Information pertaining to real-time sensor-based violations occurring during field operation of a failing integrated circuit component is used in conjunction with transition delay automatic test pattern generation (ATPG) test result information to diagnose the failing integrated circuit component. Real-time sensor-based violations can be captured during field operation at the integrated circuit component, with a sensor-based violation indicating that a sensor value generated by a sensor of the integrated circuit (such as a path margin monitor, temperature monitor, or voltage droop monitor) exceeds a sensor threshold value. Diagnosis of a failing integrated circuit component using real-time sensor-based violation information and transition delay ATPG test result information can aid in identifying a culprit path in the integrated circuit component that is likely responsible for causing the integrated circuit component failure.

An apparatus and method for efficiently managing power consumption of multiple partitions of an integrated circuit. A processing unit includes multiple partitions, each assigned to operation parameters of a respective power domain. Each of the partitions is assigned to operating parameters of a respective power domain. A power manager accesses a total power consumption budget for the multiple partitions and sends corresponding assigned power limits to the multiple partitions. A particular partition calculates a corresponding measurement of power consumption as a weighted sum of sampled signals, and performs steps to reduce power consumption when the particular partition determines the corresponding measurement of power consumption exceeds a corresponding assigned power limit. The power manager updates the assigned power limits within a first time interval. The multiple partitions calculate the power consumption measurements and perform power reduction steps within a second time interval less than the first time interval.

The present disclosure relates to burn-in apparatus, transfer method, burn-in chamber, and interchangeable frame thereof for semiconductor devices burn-in process. The burn-in apparatus comprises a burn-in chamber with an incomplete base which is to be completed and thermally insulated in cooperation with a thermal insulation base of at least one interchangeable frame which is to be removably moved into and docked in the chamber to complete the burn-in apparatus. Cooperating alignment elements are respectively arranged at the frame and the chamber, and configured to progressively and movably couple to each other to lift the frame to bring a set of burn-in boards that are supported on the frame into alignment for insertion into a set of receiving connectors in the chamber. Cooperating thermal insulation side elements may be respectively arranged at the frame and the chamber, and include complementary characteristics configured to provide a clearance gap between the thermal insulation side elements when they partially overlap each other and an abutting fit when they substantially or fully overlap each other.

The embodiment of the invention discloses a wafer testing device and a wafer testing method. The wafer testing device comprises a testing machine, a vibration meter, a probe station and a substrate. Wherein the test machine is in communication connection with the vibration meter and the wafer to be tested, the wafer to be tested is located on the substrate, the wafer to be tested and the substrate are placed on the probe station, and the vibration meter is located above the wafer to be tested; the substrate is an unsealed substrate, and the bottom of the substrate is sealed; the testing machine is used for transmitting a first signal to a crystal grain on a wafer to be tested so as to enable a vibrating membrane of the crystal grain to vibrate; the vibration meter is used for generating a second signal when the vibrating diaphragm vibrates, and the testing machine is further used for receiving the second signal and determining the state of the wafer to be tested according to the second signal and the first signal. According to the wafer testing device and the wafer testing method provided by the embodiment of the invention, vibration testing can be realized, and the testing reliability can be ensured.

A method of analyzing an integrated circuit (IC) is provided. An original netlist of the IC is obtained according to a layout and a schematic of the IC. A first simulation is performed with the original netlist to obtain electrical properties of devices in the IC. A thermal analysis is performed on the IC according to the electrical properties, to obtain a localized temperature parameter of each of the devices. A second simulation is performed according to the original netlist and the localized temperature parameter of each of the devices. The localized temperature parameter of each of the devices is determined according to a voltage and a current of the device during the first simulation.

The invention relates to the field of chips, in particular to a chip mass production test method and device, a chip and electronic equipment. The method comprises the steps that a configuration file is obtained, and the configuration file comprises test scheme data of each chip in a plurality of chips and information of each chip; generating a corresponding chip model based on the information of each chip; generating a target test model of each chip based on the chip model of each chip; obtaining a test program template corresponding to each chip, wherein the test program template corresponding to each chip corresponds to the target model of the test machine corresponding to each chip; and updating parameters in the test program template corresponding to each chip, obtaining a target test program of each chip, and importing the target test program into a test machine to test each chip. Through the embodiment of the invention, the development efficiency of the test program can be improved.

An automated test equipment comprises a tester control configured to broadcast and / or specific upload to matching module input data and / or device-specific data including keys and / or credentials and / or IDs and / or configuration information. The automated test equipment further comprises a channel processing unit configured to transform input data using device specific data in order to obtain device-under-test adapted data for testing the device under test. The channel processing unit further configured to process the DUT data using device specific data in order to evaluate the DUT data. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

The application discloses a detection driving circuit and system, wherein the detection driving circuit is connected with a power device and a sampling module, the sampling module is connected with the power device to sample current on the power device and generate a sampling signal, and the detection driving circuit comprises a control module, a driving unit, a signal detection module and a signal processing module. The detection driving circuit and system of the application sample current on the power device through the sampling module, detect whether a chip pin is accidentally suspended through an open circuit signal generation module, process signals generated by the sampling module and the open circuit signal generation module through the signal detection module and the signal processing module, and then determine whether to forcibly close the power device through the control module to ensure safety of the device and the system. The control module can automatically restart and recover to normal after a certain time without an additional external reset signal, which is simpler in application and is beneficial to reducing system cost.

A manipulator (1) comprises a holder (11) for a test head (17) that can be moved in multiple degrees of freedom between a standby position and a docking position on a docking connection (23) of a peripheral device (20) in order to carry out measurements on semiconductor components in the peripheral device (20). The holder (11) carries a data reading device, which is configured to read data relating to the peripheral device (20) in an intermediate position assumed by the holder (11) on the way from the standby position to the docking position, and a navigation unit (28) is configured to control the docking position on the basis of the read data.

The invention provides a high-temperature service life testing method and testing device. The test device comprises a test socket, a state selection circuit, a power supply circuit and a display. The test socket is coupled to the state selection circuit, the power supply circuit and the display. The test socket bears a chip to be tested. The state selection circuit receives a configuration signal. The state selection circuit adjusts the state of each pin of the test socket based on the configuration signal. The test socket sends a power control signal to the power supply circuit. The power supply circuit provides a test voltage for the test socket based on the power control signal. And the test socket executes a test operation on the to-be-tested chip based on the test code. The display displays a test result based on the check value during execution of the test operation.

A test system for a device under test (DUT) includes an arm to hold the DUT, the arm having a predetermined heat capacity to act as a heat sink for the DUT; spring pins each to secure the DUT pins to pads on a test board, each pin supporting a 90 gigahertz bandwidth; and an actuator coupled to the arm to align the DUT over a test board on a horizontal X-axis and a vertical Y-axis, the actuator providing a compressive Z-axis force on the DUT to electrically couple the DUT to the test board.

A method of testing a semiconductor device includes obtaining first data generated by testing wafers, each including a plurality of chips, the obtaining based on a plurality of first items, obtaining second data generated by testing packages, each including a packaged chip, the obtaining based on a plurality of second items, detecting correlations between the plurality of first items and the plurality of second items, based on the first data and the second data, identifying at least one first item affecting variation of the packages, based on the correlations, and testing the identified at least one first item.

A test apparatus includes: a first power source that outputs a first voltage of a predetermined magnitude or a first current of a predetermined magnitude; a first switch unit that connects a connection terminal of a device to be tested among a plurality of connection terminals of a device to be tested to the first power source; a first measurement unit that measures an electrical characteristic of a tested element of the test object corresponding to the tested element to which the first power supply is connected; and a second voltage source that outputs a second voltage of a predetermined magnitude to the connection terminal of at least one of the elements to be tested, which is different from the element to be tested of the test object, among the plurality of elements to be tested.

A method for testing radiation sensitivity includes emitting a radiation wave to a device under test, measuring a first voltage of the device under test according to the radiation wave, outputting a reference voltage to a coupling device to cause the coupling device to generate a second voltage according to the reference voltage, adjusting the reference voltage to cause the second voltage to approximate the first voltage, storing the adjusted reference voltage, outputting the second voltage to the device under test according to the adjusted reference voltage to simulate an effect of the radiation wave on the device under test, the device under test correspondingly transmitting a control signal to the coupling device after receiving the reference voltage, and determining a state of the device under test according to the control signal.