138results about "Integrated circuit testing" patented technology

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

The invention provides an integrated circuit performance testing method based on multi-dimensional parameter fusion, and belongs to the technical field of integrated circuit performance testing. S2, collecting multi-dimensional parameters; s3, data preprocessing; s4, carrying out multi-dimensional parameter fusion; and S5, performance test analysis. Through multi-parameter coverage, multi-algorithm collaboration and full-process closed loop, the problems of isolation, fragmentation and simplification of traditional testing are solved, and systematic and refined technical support is provided for performance testing of the integrated circuit.

The invention discloses a multi-source heterogeneous data processing method and system based on a test chip, and the method comprises the steps: employing a distributed message queue to access a multi-protocol data stream in real time, collecting the multi-source heterogeneous data related to a chip test, and carrying out the normalization preprocessing; performing cross-domain spatio-temporal feature alignment and mapping on the preprocessed multi-source heterogeneous data, constructing a hybrid incidence matrix based on linear correlation degree and nonlinear correlation degree, extracting three-dimensional joint features, and generating a dynamic metadata tag; generating nodes and edges by using the incidence matrix and the extracted three-dimensional joint features, constructing a parameter association graph structure, performing graph embedding training and generating an index structure, positioning Top-K candidates based on the index structure by using query features and labels, and sorting and returning a result according to a comprehensive distance; the problem that cross-domain association analysis is difficult to carry out due to the fact that the format difference of multi-source heterogeneous data generated by existing chip testing is large is solved, and the precision and efficiency of multi-source heterogeneous data processing are improved.

The invention relates to the technical field of semiconductors, and provides a chip testing method and device based on multi-physics field simulation, and the method comprises the steps: collecting the multi-physics field response data of a chip, carrying out the feature splitting and classification processing, obtaining a thermal response feature vector, an electromagnetic response feature matrix and a stress distribution sequence, and generating a thermal response map; and carrying out correlation calculation on the electromagnetic response characteristic matrix based on the thermal response map to obtain a discriminative risk grade value and an error weighting factor, then carrying out risk trend fitting analysis on the stress distribution sequence, and generating a chip performance stability evaluation index and a test adaptability score under multi-physics field interference. The chip performance stability evaluation index and the test adaptability score under the multi-physics field interference are generated by using the collected multi-physics field response data, so that comprehensive evaluation of the performance of the chip under the multi-physics field effect is realized, and the problem that the accuracy of the test result is insufficient when the chip is in a complex environment in which multiple physics fields act at the same time is solved.

The invention discloses a parameter optimization method for a chip electromagnetic fault injection test, and the method comprises the steps: collecting a large number of electromagnetic fault injection test data of a training chip, and constructing a training data set; training a plurality of models by using the constructed training data set, and establishing a mapping relationship between the electromagnetic fault injection parameter and the attack success rate; collecting a small amount of electromagnetic fault injection test data of the novel-type chip to be tested; carrying out transfer learning on the trained model by using data of a chip to be tested with a new model, and selecting an optimal model from the models after transfer learning; determining a value range of electromagnetic fault injection parameters of a chip to be detected of a new type, constructing a multi-dimensional parameter space, and generating uniformly distributed parameter combinations by using a Latin hypercube sampling method; and inputting the parameter combinations into the optimal model, predicting the attack success rate of each parameter combination, and selecting the optimal parameter combination of the electromagnetic fault injection test. According to the method, the electromagnetic fault injection parameter combination can be automatically optimized, and the manual tuning cost is reduced.

The present disclosure provides a testing apparatus, which includes a plurality of devices under test (DUTs) and an advanced process control monitor (APCM). The APCM includes a switch circuit, a control circuit, a detection circuit, and an auxiliary control circuit. The switch circuit includes a plurality of switch devices corresponding to the DUTs. The control circuit includes a plurality of control devices corresponding to the switch devices, and is configured to sequentially activate one of the switch devices during a test procedure of the testing apparatus. The detection circuit is configured to provide a first power supply voltage to a first terminal of each switch device. The auxiliary control circuit is configured to provide a second power supply voltage to a second terminal of each switch device deactivated the control circuit.

The invention discloses an ASIC special password intelligent chip aging prediction method, and relates to the field of chip aging prediction, and the method comprises the steps: carrying out the feature fusion coding through obtaining chip power supply wiring layer data and collecting environment parameters, obtaining an aging sensitivity feature vector, carrying out the fractional order aging dynamics modeling based on the aging sensitivity feature vector, and carrying out the aging prediction. Performing chip aging state prediction based on the chip aging state change equation to obtain an aging track prediction sequence, extracting an aging sensitivity feature vector component and the aging track prediction sequence to perform residual life probability evaluation, and obtaining a residual life cumulative distribution function; on the basis of the residual life cumulative distribution function, uncertainty analysis is carried out on chip aging prediction to obtain a two-factor risk index, a coupling aging rule between hardware structure weakness and environmental stress is grasped, real aging sensitive points of the chip can be accurately reflected, and accurate reference can be provided for preventive maintenance of the chip.

The invention relates to a chip testing system, device and method. The chip test system comprises a server and an embedded test device which are in communication connection. The server is configured to store a test program and load the stored test program to the embedded test device; the embedded test device is configured to run a test program so as to test one or more chips to be tested connected with the embedded test device, and the test program simultaneously tests the computing power load and the memory pressure of the chips to be tested in parallel when running. According to the chip testing system, device and method, the testing efficiency can be remarkably improved, and the real performance of the chip in an actual service scene can be accurately reflected.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

The present disclosure relates to burn-in apparatus, transfer method, burn-in chamber, and interchangeable frame thereof for semiconductor devices burn-in process. The burn-in apparatus comprises a burn-in chamber with an incomplete base which is to be completed and thermally insulated in cooperation with a thermal insulation base of at least one interchangeable frame which is to be removably moved into and docked in the chamber to complete the burn-in apparatus. Cooperating alignment elements are respectively arranged at the frame and the chamber, and configured to progressively and movably couple to each other to lift the frame to bring a set of burn-in boards that are supported on the frame into alignment for insertion into a set of receiving connectors in the chamber. Cooperating thermal insulation side elements may be respectively arranged at the frame and the chamber, and include complementary characteristics configured to provide a clearance gap between the thermal insulation side elements when they partially overlap each other and an abutting fit when they substantially or fully overlap each other.

The invention discloses a computer graphics card plugging and unplugging test device and method, relates to the technical field of graphics card plugging and unplugging tests, and aims to solve the technical problem that the graphics card plugging and unplugging tests have defects, and the computer graphics card plugging and unplugging test device comprises a test platform, a test mechanism, a plugging and unplugging assembly, a winding assembly and a stretching assembly. According to the invention, a linear and arc-shaped array plugging effect is formed through the plugging assembly by means of the clamping groove, the clamping ring and the first spring; the linear mode efficiently simulates manual plugging and unplugging, and rapid detection is achieved; performing arc-shaped mode multi-angle inclination test; the winding assembly is engaged with a pawl through ratchets and a threading channel, so that a connecting wire is effectively prevented from being wound, and a test port can move without resistance; according to the stretching assembly, a spring is replaced by an air pressure cavity, a supporting rod is flexibly adjusted and controlled through air inflation and air exhaust, line lengths are adapted to different array ports, the testing mechanism can adjust the lengths of a connecting frame and a push rod, the testing mechanism is adapted to display cards of various sizes by means of a pneumatic frame and a rubber strip, a real scene is accurately simulated, and it is powerfully guaranteed that performance detection of the display cards is comprehensive and accurate.

The invention relates to the technical field of probe detection, and discloses a wafer probe station detection path planning method, device and equipment and a probe station. The method comprises the following steps: performing boundary enhancement processing on a wafer surface image to obtain a boundary enhancement input tensor; executing dual-path feature extraction based on the boundary enhancement input tensor to obtain a first feature map including a chip boundary and a test point position; performing channel attention and space attention screening on the first feature map to obtain a second feature map; performing chip distribution feature analysis on the second feature map to obtain a test point clustering result; probe moving path planning is executed, and a global optimal path is obtained; and establishing a probe station inverse kinematics model based on the global optimal path, and calculating a probe track control sequence according to the probe station inverse kinematics model. According to the method, the wafer surface chip boundary feature extraction capability is enhanced, the stability and smoothness of the probe in the high-speed test process are ensured, and the probe positioning precision is greatly improved.

An integrated circuit and a test system including the same are provided. Provided is an integrated circuit including a plurality of first semiconductor intellectual property (IP) cores, a chip connection circuit including a first through silicon via, a second through silicon via, a receiver electrically connected to the first through silicon via, and a driver electrically connected to the second through silicon via, a multiplexing circuit configured to select an input / output (I / O) target selection signal, a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit, and a test control circuit configured to provide the I / O target selection signal to the multiplexing circuit.

The invention provides a test method for testing a semiconductor device, which comprises the following steps of: executing at least one test item in a group of test items on the semiconductor device under a first environment condition; generating, by the machine learning model, an identification result based on the test results of the at least one test item, the identification result predicting at least one test result of performing one or more test items of the set of test items on the semiconductor device under a second environmental condition; and determining whether to perform one or more test items in the set of test items on the semiconductor device under a second environmental condition based on the identification result. According to the invention, based on the test result under the first environment condition, the machine learning model is utilized to predict and obtain the corresponding identification result, so that whether the test needs to be executed again under the second environment or not is determined according to the identification result.

The invention discloses a software ecological management method of automatic test equipment and application thereof, and belongs to the technical field of integrated circuit test. The method comprises the following steps: automatically writing a version identifier containing firmware information of an upper computer and a lower computer when a test program is compiled; when the program is loaded, the system obtains the actual version of the current operating environment and compares the actual version with the version identifier; if the versions are not matched, the system interrupts program execution through consistency verification and an interlocking controller, and a version switching manager is started; and the version switching manager automatically closes the current environment according to the version identifier, searches a version information base, switches the software of the upper computer, synchronously updates the firmware of the lower computer to a target version, and restores the test after the environment verification is passed. Through binding during compiling and forced verification during loading, automatic and accurate switching of the test environment is achieved, the problems that manual switching is prone to errors and software and hardware collaboration is poor are solved, and the test risk and the maintenance cost are remarkably reduced.

The invention discloses a test machine detection system and method, a medium and computer equipment, and belongs to the field of semiconductor tests.The method comprises the steps that a program detection code is run through a test machine; sending an instruction code to the detection board by using the test mother board; executing the instruction code by using the detection board; the detection result of the instruction code executed by the detection board is displayed by using the on-off of the light-emitting diode; a detection result is fed back to the test machine through the detection plate; performing data comparison on the detection result by utilizing the test machine, and if the detection result is abnormal, displaying fail output by utilizing a test interface; and if the detection result is normal, displaying pass output by using a test interface. According to the application of the invention, each module in the system can be detected, the detection result can be synchronously displayed on the test machine and the detection board, the abnormal position and the abnormal type of the abnormal module can be rapidly locked, and the formation of a rapid abnormal processing scheme is facilitated.

The invention relates to an intelligent chip aging test system and method. According to the system disclosed by the invention, high-precision dynamic monitoring and intelligent management of a plurality of aging chips are realized through integrated power supply management, multi-channel signal acquisition, redundancy control and remote communication. The system core comprises a power supply module, a signal acquisition module, a core processing unit and a plurality of peripheral equipment interfaces; according to the method, through staged power-on time sequence control, dual redundancy check, dynamic load simulation and cloud data synchronization, the test reliability and efficiency are remarkably improved, the method is suitable for high-temperature aging screening and quality evaluation of semiconductor devices, the production cost is effectively reduced, and production process optimization is supported. The invention belongs to the technical field of electronic testing.

To provide a technique that can improve accuracy of movement correction in a stage of moving relative to a probe card.SOLUTION: An inspection device perform electrical inspection of a substrate. The inspection device includes a probe card having a plurality of probes, a stage on which the substrate is placed, the substrate is moved relative to the probe card, and the substrate is brought into contact with the plurality of probes, and a control unit that controls the movement of the stage. The control unit uses a first displacement amount based on a vertical load of the probe card and a second displacement amount based on an unbalanced load of the probe card tilted with respect to the vertical load to calculate a three-dimensional correction amount in the unbalanced load and move the stage on the basis of the calculated correction amount.SELECTED DRAWING: Figure 4

The application provides a verification method and system of a maximum likelihood sequence detection chip, the verification method comprises creating a random environment, and a random model is created in the random environment; a verification environment is created, a reference model is run in the verification environment, and a device to be tested is run in the verification environment; the random environment is run, random configuration information is generated from the random environment and is sent to the reference model; the reference model forms a test signal according to the received configuration information, and inputs the test signal to the device to be tested; the reference model generates reference data according to the configuration information and outputs the reference data to a checker, the device to be tested generates running data after running according to the test signal and outputs the running data to the checker, and the checker compares the reference data with the running data and generates a verification result. The application also provides a verification system for realizing the above method. The application can realize decoupling of generation of configuration information and the verification environment, and improves the accuracy of chip verification.

The present invention discloses a chip firmware positioning and analysis method, system, device, and electronic device, relating to the field of chip technology. The method includes: traversing all input interfaces, and repeatedly determining the magnetic field image data of the chip firmware under test corresponding to each input interface when it is a target input interface under normal working condition; based on the multiple magnetic field image data, determining the depth distribution data of different wires at the same position in the chip under test; based on the depth distribution data of different wires at the same position in the chip under test, determining the flow direction of the configuration information flow of the chip firmware under test; scanning the chip under test based on a diamond nitrogen vacancy color center sensor, and completing the positioning analysis of the chip firmware under test based on the analysis of the flow direction of the configuration information flow. The method can achieve positioning of registers within the chip under test without damaging the chip under test, thereby improving the accuracy and reliability of the firmware positioning analysis.

A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.

There is provided a test apparatus including a first power source which outputs a first voltage of predetermined magnitude or a first current of predetermined magnitude; a first switch unit which connects, to the first power source, a connection terminal of a device under test serving as a test target, among connection terminals of a plurality of devices under test; a first measuring unit which measures an electrical characteristic of the device under test serving as the test target in response to the first power source being connected to the device under test serving as the test target; and a second voltage source which outputs a second voltage of predetermined magnitude to a connection terminal of another at least one device under test which is different from the device under test serving as the test target, among the plurality of devices under test.

The present application relates to a method and a test system for testing an integrated circuit. A method for testing an integrated circuit on a test circuit board includes: performing, by a processor, a simulation of a first thermal distribution across an entire integrated circuit design; manufacturing the integrated circuit according to the integrated circuit design; and simultaneously performing a burn-in test and an automated test on the integrated circuit. The burn-in test includes a minimum burn-in temperature for the integrated circuit and a burn-in thermal distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a collection of circuit blocks and a first collection of heaters.

In order to analyze a plurality of measured values obtained by measuring a device under measurement and to effectively use the analyzed information, there is provided a recording medium having recorded thereon an analysis apparatus, the analysis apparatus including: an acquisition unit configured to acquire the plurality of measured values obtained by measuring the device under measurement via a jig; an analysis unit configured to analyze the plurality of measured values to calculate variation data which indicates a variation of a measured value in accordance with the number of times of contacts that the jig comes into contact with the device under measurement; and a management unit configured to manage a state of the jig based on the variation data.

The present invention discloses a parameter optimization method for chip electromagnetic fault injection testing, comprising: collecting electromagnetic fault injection test data from a large number of training chips to construct a training dataset; using the constructed training dataset to train multiple models and establish a mapping relationship between electromagnetic fault injection parameters and attack success rates; collecting a small amount of electromagnetic fault injection test data from a new model of chip to be tested; using the new model of chip to be tested data to perform transfer learning on the trained models, and selecting the optimal model from the transfer-learned models; determining the value range of the electromagnetic fault injection parameters for the new model of chip to be tested, constructing a multidimensional parameter space, and using the Latin hypercube sampling method to generate uniformly distributed parameter combinations; inputting the parameter combinations into the optimal model, predicting the attack success rate of each parameter combination, and selecting the optimal parameter combination for the electromagnetic fault injection test. The present invention can automatically optimize electromagnetic fault injection parameter combinations, reducing manual tuning costs.

Limiting circuitry is disclosed. In one example, the limiting circuitry provides limited electric current and / or limited electric voltage for electrically testing at least one device under test. The limiting circuitry comprises a plurality of DC-DC-converters being connected in parallel to each other, each being provided with an electric input DC voltage and each being configured for providing a converted electric output current to be forwarded to an assigned one of electric contacts for contacting the at least one device under test. A control mechanism is configured for controlling the DC-DC-converters for limiting the electric output current and / or an electric output voltage which relates to said electric output current.

The application relates to the technical field of SRAM storage and calculation anti-radiation test, and discloses an SRAM storage and calculation anti-radiation test method and system based on running state injection, which comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; model quantization compilation, sensitivity analysis and physical bit candidate generation; running state injection plan generation and test case loading; running state execution, disturbance injection and synchronous monitoring collection; multi-source triggering, weight reading back and fault decoupling decision; anti-radiation performance quantitative evaluation, degradation curve construction and report output. The system and the method correspond to each other. The application constructs a hardware-in-the-loop running state injection and online evaluation technology, and realizes the technical problems of a guided disturbance / equivalent radiation injection based on weight bit level sensitivity and logic-physical mapping.

The invention relates to the technical field of chip failure analysis, in particular to a chip failure analysis path hierarchical decision and intelligent management and control method, which comprises the following steps: determining whether to perform data optimization or not according to a path abnormal frequency ratio of a target analysis model to obtain an optimized target analysis model; in the data optimization, a supplementary strategy of associated data supplementation is adopted, and whether the supplementary strategy comprises failure analysis supplementation or not is determined according to the high-frequency associated abnormal chip data proportion; in the failure analysis supplement, an outlier parameter is directly determined according to a related reference value or whether the outlier parameter is an outlier parameter or not is secondarily determined according to a deviation reproduction frequency ratio and a parameter emergence coefficient, data supplement is carried out for each outlier parameter, and whether global disturbance analysis supplement is carried out or not is determined according to a global abnormal coefficient. The analysis efficiency and the result reliability can be improved.