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7results about "Integrated circuit testing" patented technology

Integrated circuit component diagnosis using real-time sensor-based violation information

PendingUS20260140166A1Integrated circuit testingVoltage droopAutomatic test pattern generation
Information pertaining to real-time sensor-based violations occurring during field operation of a failing integrated circuit component is used in conjunction with transition delay automatic test pattern generation (ATPG) test result information to diagnose the failing integrated circuit component. Real-time sensor-based violations can be captured during field operation at the integrated circuit component, with a sensor-based violation indicating that a sensor value generated by a sensor of the integrated circuit (such as a path margin monitor, temperature monitor, or voltage droop monitor) exceeds a sensor threshold value. Diagnosis of a failing integrated circuit component using real-time sensor-based violation information and transition delay ATPG test result information can aid in identifying a culprit path in the integrated circuit component that is likely responsible for causing the integrated circuit component failure.
Owner:INTEL CORP

Method of analyzing integrated circuit and package chip

PendingUS20260147035A1Integrated circuit testingSoftware engineeringSchematic maps
A method of analyzing an integrated circuit (IC) is provided. An original netlist of the IC is obtained according to a layout and a schematic of the IC. A first simulation is performed with the original netlist to obtain electrical properties of devices in the IC. A thermal analysis is performed on the IC according to the electrical properties, to obtain a localized temperature parameter of each of the devices. A second simulation is performed according to the original netlist and the localized temperature parameter of each of the devices. The localized temperature parameter of each of the devices is determined according to a voltage and a current of the device during the first simulation.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Manipulator, docking method therefor and data carrier usable in the method

PendingEP4762368A1Integrated circuit testing
A manipulator (1) comprises a holder (11) for a test head (17) that can be moved in multiple degrees of freedom between a standby position and a docking position on a docking connection (23) of a peripheral device (20) in order to carry out measurements on semiconductor components in the peripheral device (20). The holder (11) carries a data reading device, which is configured to read data relating to the peripheral device (20) in an intermediate position assumed by the holder (11) on the way from the standby position to the docking position, and a navigation unit (28) is configured to control the docking position on the basis of the read data.
Owner:ESMO

Automated test equipment and methods using device-specific data

ActiveCN115605767BDigital variable displayTransmissionData packProcessing element
An automated test equipment comprises a tester control configured to broadcast and / or specifically upload input data and / or device specific data, including keys and / or certificates and / or IDs and / or configuration information, to a matching module. The automated test equipment further comprises a channel processing unit configured to transform the input data using the device specific data to obtain device under test adapted data for testing a device under test. The channel processing unit is further configured to process the DUT data using the device specific data to evaluate the DUT data. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.
Owner:ADVANTEST CORP

Margin tester and margin test method

ActiveJP7867770B2Error detection/correctionIntegrated circuit testing
To make it possible for a user to easily de-embed an adapter.SOLUTION: A margin tester 202 comprises: an identification reader 204 for reading an adaptor unique identifier 206 of an adaptor 208; an interface configured to connect to a device 212 under test through the adaptor 208; and a controller 104 having a processor configured to assess a margin of the test device 212 under test. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor unique identifier 206.SELECTED DRAWING: Figure 2
Owner:TEKTRONIX INC

Electrical test structure and electrical test method

ActiveCN114895170BContinuity testingIntegrated circuit testingElectrical connectionStructural engineering
The present application relates to an electrical test structure and an electrical test method. The electrical test structure comprises: a plurality of test components, each of which comprises a test structure and a protection structure electrically connected to the test structure; and a plurality of pads, each of which is connected to two test components and each of which can be connected to two test components at the same time, and the protection structure in each test component is used to control whether the test structure and the pad are conductive. The present application can effectively save the number of pads, improve the anti-interference of the test components themselves, and reduce the interference between the test structures.
Owner:YANGTZE MEMORY TECH CO LTD

Inspection method, inspection device, and program

To provide a technique that allows a probe to accurately contact an electrode formed on an object to be inspected.SOLUTION: An inspection method performed by an inspection device including a mounting table on which an object to be inspected is placed, and a probe card provided with a probe used for inspecting the object to be inspected includes steps of: bringing the probe into contact with an electrode on the basis of a first offset value; setting a second offset value on the basis of a needle mark area formed by bringing the probe into contact with the electrode on the basis of the first offset value; and bringing the probe into contact with the electrode on the basis of the second offset value.SELECTED DRAWING: Figure 4
Owner:TOKYO ELECTRON LTD