An accelerator structure and loop unrolling method for binarized neural network

Abstract

The invention discloses an accelerator structure and a loop expansion method for a binary neural network. Aiming at a hardware accelerator structure with a weight value of 1 bit and a feature value of n bits, the invention includes hardware structure design of the accelerator and a method for binarization Neural network optimized loop unrolling structure and storage order of weights and eigenvalues ​​in SRAM. The hardware structure includes weights, eigenvalue storage SRAM, dedicated convolution calculation module and addition tree unit. The dedicated convolution module designs a new convolution calculation method, and the addition tree ensures the pipeline operation of the data. The combination of the loop expansion method used in the present invention and the accumulator can make the accelerator have very good scalability, and the size of the block K can be freely determined according to the complexity of the network and hardware resources without changing the control logic of the circuit. Cooperating with this loop expansion method, the present invention also proposes a storage order of weights and feature values ​​to simplify the access logic.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an accelerator structure and a loop unrolling method for a binary neural network. Background technique [0002] The convolutional neural network algorithm is a research hotspot in recent years. The convolutional neural network algorithm is a computing system designed by people through the simple imitation of brain neurons and combined with a large amount of statistical knowledge. It is mainly divided into two parts, the training stage and the inference stage. In the training stage, a large number of data sets are used to adjust the weights of each node in the network. In the inference stage [0003] In the segment, the picture or other signal to be processed is input into the system, and the characteristic value of the signal can be obtained after calculation. Convolutional neural network algorithms have greater advantages over traditional algorithms in application d...

AI Technical Summary

Problems solved by technology

However, the traditional general-purpose processor (CPU) can no longer meet the hardware requirements of today's neural network algorithms. Therefore, designing a new type of neural network accelerator dedicated to it is also a hot research topic at present.

[0004] The binary neural network is a direction of weight coefficient compression in the acceleration technology. In order to reduce the storage space of the coefficient and improve the operation speed, the weight value is from the initial 32bit floating point number to the 8bit fixed point number to the 1bit number involved in the present invention. Therefore, the previous general-purpose accelerators for ordinary convolutional neural network algorithms will have a large amount of redundant computing resources when accelerating the binary network, and cannot achieve the best efficiency. The classic XNOR-POPCONUT structure binary accelerator uses the same OR operation and The pop count operation is used to replace multiplication and accumulation, but it can only be used on algorithms with 1-bit weight and input. Therefore, it is necessary to design a hardware accelerator and design appropriate control logic for algorithms with 1-bit weight and n-bit input.

Images