Optimization of floating point complex vector summation based on BWDSP chips

Abstract

The invention belongs to the field of optimization of the underlying function for digital signal processors and discloses an optimization of floating point complex vector summation based on high-performance general signal processor BWDSP chips; the floating point complex vector summation is the summation of a first floating point complex vector and a second floating point complex vector; the summation of the first floating point complex vector and a second floating point complex vector is circulation of summation of multi-time floating point complex numbers; each summation process of the floating point complex numbers comprises instruction parallel optimization based on BWDSP chips, that is, optimization of simultaneous control of more than one operation units to execute a same operation by one instruction; optimization based on circulation, that is, multiple times of optimization of the same loop code in a loop; optimization based on software pipeline, that is, optimization of multiple times of execution of same circulation code parallel intersection. The hardware resource of BWDSP chips can be fully utilized to obtain efficient underlying functions.

Description

technical field [0001] The invention belongs to the field of bottom function optimization of digital signal processors, and in particular relates to an optimization method for realizing the summation of floating-point complex vectors based on a high-performance general-purpose signal processor BWDSP chip. Background technique [0002] With the rapid development of large-scale integrated circuits and digital computers, digital signal processors have gradually developed to meet the needs of high-speed real-time signal processing tasks. Independent research and development of DSP processor chips has gradually become an important issue in the development of digital signal processing technology in my country. In this context, a research institute has launched a series of high-performance DSP processors BWDSP. This DSP is completely independently developed from the architecture to the instruction system, to the design and implementation, and the development environment supporting ...

AI Technical Summary

Problems solved by technology

[0004] To provide software support for the development of BWDSP, the development language used is C language or assembly language. Considering the improvement of the operation efficiency of the function, although the C language is easy to read and has good portability, it is not convenient for direct control of the hardware system. Give full play to the characteristics of the DSP chip itself, so the assembly language is selected to complete the design of the library function to ensure the maximum utilization of processor hardware resources

However, the assembly language compiled directly from the C language does not combine the hardware characteristics of the DSP chip, and there are certain defects.

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