39results about How to "Improve bus utilization" patented technology

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits / cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits / cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

The invention discloses a network scheduling algorithm for a CAN (controller area network) bus master-slave answer mode protocol; the network scheduling algorithm is used for message scheduling in a CAN bus network which adopts a master-slave answer mode application protocol for network communication. According to the scheduling algorithm, when a time-triggered scheduling list is created, constraint conditions that requests and answer messages are placed alternately, request messages of the same destination ID are not arranged in adjacent columns of the same row of the scheduling list are adopted for creating the scheduling list in an alternate type bin packing algorithm. A genetic algorithm is improved for optimizing the exclusive time window of the scheduling list, so that the bus use ratio is improved. Node messages in the network are subjected to periodical statistics, the scheduling list is dynamically updated, and reasonable use of resources is realized. According to the scheduling algorithm, the use ratio of network buses can be improved, waiting time lapse of messages can be reduced, messages can be reasonably scheduled, and defects of an existing network scheduling algorithm when a master-slave answer mode is adopted are overcome.

A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

A mechanism is provided for reorderingReordering bus transactions to increaseincreases bus utilization in a computer system in whichwhere a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In; in another embodiment, the system is more loosely coupled with only masters beingare ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would,result in deadlock if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is refused if requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the further transactionstransaction is killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis. In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.

The embodiment of the present application provides a data transmission method, device, and system. The method includes: obtaining data transmitted by M lanes included in the data bus in each clock cycle to obtain M data; Store data to the preset buffer; when the data length between the last data read position and the last data storage position in the preset buffer is greater than or equal to the preset data length, read M valid data from the preset buffer , the preset data length is M multiples of the maximum data length transmitted by one lane; the read M effective data are transmitted through M lanes respectively. By applying the technical solution provided by the embodiment of the present application, the bus utilization rate of the multi-lane bus system can be improved, and the data transmission efficiency of the entire multi-lane bus system can be improved without changing the data structure of the upstream module and the downstream module.

In the embodiment, the invention discloses a data transmission method, a data transmission system and a CPU interface controller. The method comprises the steps that: after data transmitted through a bus is received, the data is stored; and the stored data is transmitted to a corresponding display unit through the time sequence of a CPU interface. With the invention, the bus transmission functionand the CPU transmission function do not need to be finished in one-time data transmission, but bus data transmitted at high-speed is stored to ensure that the bus resource can be released in time, thereby finishing other work in the system; then the CPU interface makes low-speed transmission to the stored data to ensure that the bus transmission and the CPU transmission are respectively finished, thereby effectively improving the bus utilization rate and the working efficiency of the system under the condition of failing to change the transmission rate of the CPU interface.

The invention relates to a system for increasing the speed of route lookup in the technical field of computer network technology. The system comprises a drive module, an interface module, an initialization module, a route-storing module, a human-computer interaction module and a lookup module, wherein the drive module is connected with the human-computer interaction module to transmit drive information; the human-computer interaction module is connected with the interface module to transmit mutual information; the interface module is connected with the initialization module to transmit initialization information; the interface module is connected with the lookup module to transmit mutual information; the lookup module is connected with the route-storing module to transmit route information to be looked up; and the lookup module comprises a dividing submodule, an addressing submodule, a reading submodule, a writing submodule and a judging submodule. The average lookup speed of the system is up to 50M / s; the complexity of the system is low; the occupied data space is small; binary tree structure is not used so that the addition and deletion of memory space become more flexible; and the system is applicable to small-capacity route storage, and when a high-capacity storage hardware device exists outside the system, the system can also realize route storage.

The present invention discloses an inverter and its PWM modulation method, where the PWM modulation method includes providing a modulation signal, obtaining an amplitude value of a third harmonic according to a modulation ratio of the modulation signal, injecting the third harmonic into the modulation signal and generating a PWM drive signal, and inputting the PWM drive signal into the control end of an inverter switch tube to control turning on or turning off of the inverter switch tube. Through the foregoing method, the present invention can achieve that the inverter has maximum bus utilization and minimum common-mode voltage to avoid generating relatively high ground leakage current and relatively serious electromagnetic interference.