39results about How to "Improve bus utilization" patented technology

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits / cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits / cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

The invention discloses an inverter and a pulse width modulation (PWM) method thereof. The PWM method comprises the following steps of: providing a modulation signal; acquiring the amplitude of third harmonic according to the size of a modulation ratio M of the modulation signal; injecting the third harmonic into the modulation signal to generate a PWM driving signal; and inputting the PWM driving signal into a control end of an inverter switching tube to control the turn-on or turn-off of the inverter switching tube. In the mode, the invention has the advantages that the inverter has the highest generatrix utilization rate and lowest output common-mode voltage, and high earth leakage current and electromagnetic interference are avoided.

A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In another embodiment, the system is more loosely coupled with only masters being ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the further transactions is killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis. In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.

The invention discloses an implementation method for the time-triggered communication bus of an aeroengine distributed control system and belongs to the field of aeroengine control technique. The method comprises the steps of A, implementing the physical layer of a TTCAN bus controller; B, implementing the data link layer of the TTCAN bus controller; C, implementing the time-triggered system of the TTCAN bus controller; and D, implementing the experimental platform of an aeroengine distributed control system. According to the technical scheme of the above method, a two-level TTCAN bus-contained controller is adopted, so that the rates of local timers at all bus nodes of an aeroengine in high-temperature and high-vibration environments are ensured to be synchronized. The real-time performance and the security are ensured, and the bus utilization rate is improved.

The invention discloses a FPGA heterogeneous acceleration system comprising a FPGA and a PCIe drive end; the FPGA comprises DMAs of a first preset number and a request queue corresponding to each DMA; the PCIe drive end comprises service threads of a second preset number; the service thread is used for checking whether the corresponding request queue is empty or not, and if yes, a new request is added to the corresponding request queue, and the corresponding DMA is started for data transmission; the DMA is used for processing requests in sequence in the corresponding request queue, and an interrupt is sent to the PCIe drive end after each request is processed so as to prompt the data transmission is finished; the DMAs can commonly carry out data transmission, thus maximumly improving PCIe bus utilization rate, improving data transmission speed, and ensuring a reliable speed for a heterogeneous acceleration algorithm; the invention also discloses a FPGA heterogeneous acceleration data transmission method and the FPGA having said benefits.

The invention discloses a network scheduling algorithm for a CAN (controller area network) bus master-slave answer mode protocol; the network scheduling algorithm is used for message scheduling in a CAN bus network which adopts a master-slave answer mode application protocol for network communication. According to the scheduling algorithm, when a time-triggered scheduling list is created, constraint conditions that requests and answer messages are placed alternately, request messages of the same destination ID are not arranged in adjacent columns of the same row of the scheduling list are adopted for creating the scheduling list in an alternate type bin packing algorithm. A genetic algorithm is improved for optimizing the exclusive time window of the scheduling list, so that the bus use ratio is improved. Node messages in the network are subjected to periodical statistics, the scheduling list is dynamically updated, and reasonable use of resources is realized. According to the scheduling algorithm, the use ratio of network buses can be improved, waiting time lapse of messages can be reduced, messages can be reasonably scheduled, and defects of an existing network scheduling algorithm when a master-slave answer mode is adopted are overcome.

A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

The invention relates to a bus transfer optimization method based on Beidou positioning and a passenger flow. The method comprises the steps of measuring and acquiring bus data by use of a Beidou navigation satellite system; constructing an urban bus network according to a basic theory and algorithm of a complex network; and giving an optimal scheme in combination with the bus network. The methodadopts the basic concept that information data of each bus line and all bus stops thereof, a distance between two bus and card swiping data of a bus are firstly collected; determining weights of related parameters and edges; respectively establishing a complex network model according to user demands; and analyzing and calculating and determining a final bus taking scheme according to adjacent matrixes corresponding to different models by use of an Floyd algorithm.

The invention discloses a software radio platform based on an SCA (Software Communications Architecture). The platform includes a main control CPU, a load agent FPGA, a DDR, an FLASH and a waveform component FPGA. The load agent FPGA includes the following program modules: an SRIO_Driver module, an HAL_LD-PD module, an HAL_LD-APP module, an MAIN_CTRL module, an FLASH_CTRL module, a DDR_CTRL moduleand a K7_CFG module. The load agent FPGA is responsible for configuring the waveform component FPGA. The problem that IO / component / link adaptation is difficult and reconstruction is liable to fail due to general FPGA dynamic reconfiguration is effectively handled.

The invention discloses a bus switch method based on CAN redundance, comprising the steps: 1) judging nodes are sending nodes or receiving nodes; if being the sending nodes, entering the step 2); if being the receiving nodes, entering the step 5); 2) judging whether the sending nodes are sent overtime; if yes, entering the step 3); if not, entering the step 4); 3) retransmitting by a switch bus; 4) monitoring the sending nodes until overtime or receiving response frame of the receiving nodes; 5) judging whether the receiving nodes are sent overtime; if yes, entering the step 6); if not, entering the step 7); 6) using a broadcast switch bus to inform other node switch buses to retransmit data; 7) receiving the response frame sent by the nodes as the response for the sending nodes, and showing that the data is successfully sent and received. The method can ensure the reliable accuracy and real-time property of data reception.

The invention relates to a fiber communication protocol used for a distributed controller. An M node writes an instruction frame signal into an M instruction frame queue zone and sends the instruction frame signal to an S1 node; the S1 node stores an instruction frame into the M instruction frame queue zone and forwards the instruction frame to a next S node, and by parity of reasoning, an Sn node sends the instruction frame to the M node and covers the M instruction frame queue zone; for the S1 node, a data frame is directly transmitted to a next node; for the Sn (n is greater than or equal to 2) node, the data frame of a previous node and the data frame of a current node are received to form a new message queue, and the new message queue is transmitted to the next node; by parity of reasoning, the message queue of the Sn node comprises the data frames of all S nodes and is transmitted to the M node; and after the M node detects a data frame signal, the data frame is written into each node data frame queue zone of the message queue, and the data frame and the previous received and covered instruction frame form a complete message queue. In one instruction period, data interaction between a master controller node and each slave controller node is realized.

The invention relates to a terminal communication acquisition front-end system. The terminal communication acquisition front-end system comprises a business machine, a data gateway, a gateway server, a database server and a one-card platform; the business machine comprises a micro-processor and a CAN bus interface connected with the micro-processor; a card read-write device and an identification card printer are also connected with the micro-processor; the CAN bus interface of the business machine is connected with the data gateway through a CAN bus; the data gateway is connected with the gateway server and the database server through an Ethernet; and the data gateway communicates with the gateway server in a TCP communication manner. The disadvantage that the data transmission real-time requirement cannot be ensured due to the fact that the existing bus network always has a communication fault can be effectively avoided.

The invention relates to an Ethernet-based intelligent terminal interactive system, which comprises a master station and at least two terminals, wherein the master station sends a command to the terminals and receives data uploaded by the terminals; the at least two terminals are connected to the master station to realize information transmission; the terminal and the adjacent terminal are connected in an Ethernet mode to form an Ethernet local area network, so that information sharing between the terminals is realized; and one or more terminals serve as relay stations and are connected to themaster station and are used for forwarding the command or transmitting the data. Compared with the prior art, through the intelligent terminal interaction system provided by the invention, the stability of data transmission can be effectively improved, the pressure of the master station is reduced, and the stability of the system is improved.

In the embodiment, the invention discloses a data transmission method, a data transmission system and a CPU interface controller. The method comprises the steps that: after data transmitted through a bus is received, the data is stored; and the stored data is transmitted to a corresponding display unit through the time sequence of a CPU interface. With the invention, the bus transmission function and the CPU transmission function do not need to be finished in one-time data transmission, but bus data transmitted at high-speed is stored to ensure that the bus resource can be released in time, thereby finishing other work in the system; then the CPU interface makes low-speed transmission to the stored data to ensure that the bus transmission and the CPU transmission are respectively finished, thereby effectively improving the bus utilization rate and the working efficiency of the system under the condition of failing to change the transmission rate of the CPU interface.

A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

The embodiment of the invention provides a data transmission method, device and system, and the method comprises the steps of obtaining data transmitted by M lanes included in a data bus in each clock period, and obtaining M pieces of data; storing valid data in the M pieces of data to a preset buffer area; when the data length between the last data reading position and the last data storage position in the preset buffer area is larger than or equal to the preset data length, reading M valid data from the preset buffer area, wherein the preset data length is M times of the maximum data length transmitted by one lane; and respectively transmitting the read M effective data through the M lanes. By applying the technical scheme provided by the embodiment of the invention, the bus utilization rate of the multi-lane bus system can be improved, so that the data transmission efficiency of the whole multi-lane bus system is improved on the basis of not changing the data architecture of the upstream module and the downstream module.

The invention relates to an explosive-proof electromagnet module based on CAN communication. The explosive-proof electromagnet modulecomprises a plurality of groups of explosive-proof electromagnets, each group of explosive-proof electromagnets comprises an explosive-proof electromagnet body and an explosive-proof wiring device, and each explosive-proof wiring device comprises an explosive-proof wiring box, a CAN control module and two air plug modules. One end of the CAN control module is connected with the two air plug modules through a CAN interface circuit, every two adjacent groups of flame-proof electromagnets are connected through the adjacent aviation plug modules in a CAN line cascading mode, and one end of the CAN control module is connected with the flame-proof electromagnet body. The CAN control module converts a control instruction into two PWM control signals and outputs the two PWM control signals to the flame-proof electromagnet body, so that the proportional control over the valve elements of the explosion-proof electromagnetic valve group of the explosion-proof electromagnet body in the group is achieved. The explosion-proof electromagnet module is further connected with an explosion-proof vehicle-mounted unit and an intrinsic safety operation unit in sequence, so that the remote intelligent control is achieved. According to the present invention, wiring harnesses are reduced, the wiring process is simplified, and maintenance is convenient.

The invention discloses a method and device for carrying out data communication with a low speed network device. The method comprises following steps of establishing a low speed network task for processing a low speed network message in the communication process of the low speed network device and a high speed network device, wherein the low speed network task comprises a low speed network message sending subtask and a low speed network message receiving subtask; successively carrying out the low speed network message sending subtask and the low speed network message receiving subtask, wherein the low speed network message sending subtask is used for sending the low speed network message to the low speed network device, and the low speed network message receiving subtask is used for receiving the low speed network message processed by the low speed network device. Through adoption of the technical scheme, the technical problem that in the prior art, when the low speed network device communicates with the high speed network device, it is easy to result in bus conflict of the low speed network is solved.

A mechanism is provided for reorderingReordering bus transactions to increaseincreases bus utilization in a computer system in whichwhere a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In; in another embodiment, the system is more loosely coupled with only masters beingare ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would,result in deadlock if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is refused if requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the further transactionstransaction is killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis. In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.

The embodiment of the present application provides a data transmission method, device, and system. The method includes: obtaining data transmitted by M lanes included in the data bus in each clock cycle to obtain M data; Store data to the preset buffer; when the data length between the last data read position and the last data storage position in the preset buffer is greater than or equal to the preset data length, read M valid data from the preset buffer , the preset data length is M multiples of the maximum data length transmitted by one lane; the read M effective data are transmitted through M lanes respectively. By applying the technical solution provided by the embodiment of the present application, the bus utilization rate of the multi-lane bus system can be improved, and the data transmission efficiency of the entire multi-lane bus system can be improved without changing the data structure of the upstream module and the downstream module.

The invention discloses a bus protocol based on TTCAN communication. According to the bus protocol, a TTCAN time triggering mode is adopted for communication; and a slave station sends current position information of a motor to a master station every 10ms, each data packet in the position information comprises eight bytes, the first four bytes are return values, the fifth byte is a state value, the sixth byte is a motor circuit grade value, and the last two bytes are null. According to the bus protocol, a TTCAN communication protocol is improved, the protocol is simplified, time windows can bereduced, communication loads are simplified, and the reliability and speed of load transmission are improved.

The invention provides a communication architecture of dynamic random access memory system, which is based on a double-rate synchronous dynamic random access memory standard and comprises a dynamic random access memory chipset, a data input / output switch circuit and a memory controller, the data input / output switch circuit is a switch array used for controlling a data input and output selection signal and a data input and output signal direction of each dynamic random access memory chip in the dynamic random access memory chip group, and the switch array is used for adjusting a phase shifter; the memory controller is used for independently controlling each dynamic random access memory chip through different chip selection signals so as to realize the movement of data from the read operation of the source address dynamic random access memory chip to the write operation of the target address dynamic random access memory chip; and the memory controller is used for controlling the switch array of the data input / output switch circuit so as to establish data paths among different chips.

The invention discloses CAN-BUS application to an ARM-based mining water pump motor control system. According to the invention, a CAN bus and a plurality of water pump motor measurement and control substations are arranged. Data collected by the water pump motor measurement and control substations are transmitted to a well-above monitoring control personnel unit through the CAN bus and a CAN-Ethernet communication gateway to carry out calculation and analyzing. According to the system, the CAN bus is used at an equipment layer to carry out communication. With utilization of the real-time processing capability of the ARM, various data parameters of the water pump motor are collected, calculated and analyzed based on data communication of the measurement and control substations and the well-above monitoring control personnel unit. Once various data are abnormal, acousto-optic alarming is carried out; and various state data are transmitted to the well-above monitoring control personnel. Therefore, the emergency dealing capability is substantially improved; and the accident occurrence probability is reduced.

The invention provides a redundancy system, a redundancy management method and a readable storage medium. The redundancy system comprises a first redundancy equipment and at least one second redundancy equipment. The first redundancy equipment comprises a first controller and a first programmable module; the first controller is connected with the first programmable module through a communication interface; the first programmable module performs data transmission with the at least one second redundancy equipment and a downlink execution unit through at least one redundancy bus; wherein at least two kinds of data are respectively transmitted between the first programmable module and the at least one second redundancy equipment and between the first programmable module and the downlink execution unit through the same redundancy bus in different time periods. The programmable module serves as a function extension peripheral of the controller, the data processing speed and the system flexibility can be improved, in addition, at least two kinds of data are transmitted in different time periods through the same redundancy bus, the bus utilization rate can be improved, and the wiring complexity is simplified.

The invention discloses a method for effectively utilizing memory bandwidth. A main control chip is included, a random storage control module is arranged in the main control chip, the random storage control module is provided with a writing unit and a reading unit which are respectively connected with a random storage component. According to the method, the static memory space is used as a write-in and read-out cache, so the defect of frequency difference or random memory delay can be made up, and the bus utilization rate of the main control end is improved.

In the embodiment, the invention discloses a data transmission method, a data transmission system and a CPU interface controller. The method comprises the steps that: after data transmitted through a bus is received, the data is stored; and the stored data is transmitted to a corresponding display unit through the time sequence of a CPU interface. With the invention, the bus transmission functionand the CPU transmission function do not need to be finished in one-time data transmission, but bus data transmitted at high-speed is stored to ensure that the bus resource can be released in time, thereby finishing other work in the system; then the CPU interface makes low-speed transmission to the stored data to ensure that the bus transmission and the CPU transmission are respectively finished, thereby effectively improving the bus utilization rate and the working efficiency of the system under the condition of failing to change the transmission rate of the CPU interface.

The invention relates to an electric power measuring instrument based on CAN bus communication, which specifically comprises a central processing unit, a communication circuit, a power supply circuit,a measuring circuit, a driving circuit and a key and display circuit; the central processing unit is connected with the communication circuit through an internal serial port of the central processingunit. The central processing unit is connected with the power supply circuit through an internal power supply port of the central processing unit; the central processing unit is connected with the measuring circuit through an internal control port of the central processing unit, the central processing unit is connected with the driving circuit through an internal bus port of the central processing unit, and the key and display circuit is connected with an internal I / O port of the central processing unit and a driving bus of the driving circuit. According to the embodiment of the invention, the CAN bus is used for communication; and the electric power measuring instrument has the advantages of high transmission rate, long transmission distance, high electromagnetic interference resistanceand the like.

The invention relates to a system for increasing the speed of route lookup in the technical field of computer network technology. The system comprises a drive module, an interface module, an initialization module, a route-storing module, a human-computer interaction module and a lookup module, wherein the drive module is connected with the human-computer interaction module to transmit drive information; the human-computer interaction module is connected with the interface module to transmit mutual information; the interface module is connected with the initialization module to transmit initialization information; the interface module is connected with the lookup module to transmit mutual information; the lookup module is connected with the route-storing module to transmit route information to be looked up; and the lookup module comprises a dividing submodule, an addressing submodule, a reading submodule, a writing submodule and a judging submodule. The average lookup speed of the system is up to 50M / s; the complexity of the system is low; the occupied data space is small; binary tree structure is not used so that the addition and deletion of memory space become more flexible; and the system is applicable to small-capacity route storage, and when a high-capacity storage hardware device exists outside the system, the system can also realize route storage.