A data transmission method, device and system

Abstract

The embodiment of the present application provides a data transmission method, device, and system. The method includes: obtaining data transmitted by M lanes included in the data bus in each clock cycle to obtain M data; Store data to the preset buffer; when the data length between the last data read position and the last data storage position in the preset buffer is greater than or equal to the preset data length, read M valid data from the preset buffer , the preset data length is M multiples of the maximum data length transmitted by one lane; the read M effective data are transmitted through M lanes respectively. By applying the technical solution provided by the embodiment of the present application, the bus utilization rate of the multi-lane bus system can be improved, and the data transmission efficiency of the entire multi-lane bus system can be improved without changing the data structure of the upstream module and the downstream module.

Description

technical field [0001] The present application relates to the field of network technology, in particular to a data transmission method, device and system. Background technique [0002] Many modules in the network are connected by a multi-lane data bus (hereinafter referred to as multi-lane bus). The specific system architecture is as follows: the upstream module is connected to an asynchronous First Input First Output (FIFO) module through a multi-lane bus, and the asynchronous FIFO module is connected to a downstream module through a multi-lane bus. The upstream module sends data to the downstream module through the multi-lane bus and the asynchronous FIFO module. [0003] The bus utilization rate of the multi-lane bus system depends on the bus utilization rate between the asynchronous FIFO module and the downstream module, and the bus utilization rate between the FIFO module and the downstream module depends on the bus utilization rate between the upstream module and the ...

AI Technical Summary

Problems solved by technology

[0004] However, in the multi-lane bus system, when the upstream module sends data through the multi-lane bus, invalid data is likely to be transmitted on some lanes in the multi-lane bus within one clock cycle, which makes the bus utilization of the entire multi-lane bus system The rate is low, which leads to low data transmission efficiency of the entire multi-lane bus system

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