The invention relates to the technical field of
radar signal processing, in particular to a universal interface architecture design method of a 40G
Ethernet for
radar signal processing, a bottom driver of the architecture is a DPDK, a universal
interface design is provided, and a user can realize definition and play only according to a definition
declaration port. During operation, cross-thread direct connection of the functional entity is realized through the
shared memory annular
queue, and the functional entity autonomously screens required data, so that intermediate links are eliminated. The architecture supports unpacking and restructuring of oversized and giant data packets and realizes receiving and transmitting of data with any
byte length. The method comprises
universal function interface design,
application protocol header design, data group packet sending design, receiving memory design, receiving single packet
data processing design, receiving giant packet
data processing design and receiving multi-node synchronous
data processing design. According to the method, through protocol packaging, zero-copy optimization and two-stage cache design, the difficulty of synchronization of giant
packet processing and multiple computing nodes under the 40G
Ethernet is solved.