Bus transaction reordering in a computer system having unordered slaves

Abstract

A mechanism is provided for reorderingReordering bus transactions to increaseincreases bus utilization in a computer system in whichwhere a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In; in another embodiment, the system is more loosely coupled with only masters beingare ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would,result in deadlock if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is refused if requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the further transactionstransaction is killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis. In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.

Description

[0001]Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,996,036. The reissue applications are U.S. patent application Ser. No. 10 / 006,939 (now U.S. Pat. No. Re. 38,428) and U.S. patent application Ser. No. 10 / 669,119 (the present application). The present application is a continuation of U.S. patent application Ser. No. 10 / 006,939 filed Nov. 30, 2001 (now U.S. Pat. No. Re. 38,428), which is a continuation-in-part of U.S. patent application Ser. No. 08 / 432,622, filed May 2, 1995, now abandoned. FIELD OF THE INVENTION[0002]The present invention relates to computer architecture, in particular to computer architecture for small computer systems such as personal computers.STATE OF THE ART[0003]The PowerPC computer architecture, co-developed by Apple Computer, represents a departure from prior-generation small computer architectures. PowerPC machines currently sold by Apple are based largely on the Motorola MPC601 RISC microprocessor. Other relate...

AI Technical Summary

Benefits of technology

The patent is about a mechanism for improving the use of a computer system's bus. It involves reordering bus transactions to increase efficiency. The system uses a queuing structure to handle requests from masters and slaves. When an address bus grant is given, a record is entered in the structure, which includes a master queue and a slave queue. A matching circuit produces match bits to identify a master entry, and a data arbitration circuit generates data bus grant signals for the masters and a multibit signal for the slaves. These signals enable the system to prioritize transactions and optimize bus use. The technical effects of this mechanism include increased overall bus utilization and improved system performance.

Problems solved by technology

However, external hardware can further decouple the address and data buses, allowing the data tenures to occur out of order with respect to the address tenures.

Although ordered masters and slaves, as opposed to unordered masters and slaves, provide an overall simplification to system architecture, they can lead to deadlocks when there are conflicting completion dependencies.

Deadlock occurs in a computer system when one resource cannot complete an access to another resource, and the access blocks other resources from performing transactions on the bus.

Livelock occurs in a computer system when one resource cannot complete an access to another resource, does not block resources from performing transactions on the bus, but no forward progress can be made due to the resource's inability to complete its access.

Due to the plethora of design methodologies and implementations utilized by expansion card vendors, systems are most prone to deadlocks and livelocks when there is an expansion bridge in the system.

Unfortunately, when they communicate with each other this causes a conflict, and if one does not back off its access, the end result is deadlock or livelock.

This conflict of interest could result in deadlock.

This behavior also means that the PCI2PCI bridge assumes that it does not have to be backed off, and any communication between the ARBus and a target behind the PCI2PCI bridge could result in deadlock.

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