Communication architecture of dynamic random access memory system

Abstract

The invention provides a communication architecture of dynamic random access memory system, which is based on a double-rate synchronous dynamic random access memory standard and comprises a dynamic random access memory chipset, a data input / output switch circuit and a memory controller, the data input / output switch circuit is a switch array used for controlling a data input and output selection signal and a data input and output signal direction of each dynamic random access memory chip in the dynamic random access memory chip group, and the switch array is used for adjusting a phase shifter; the memory controller is used for independently controlling each dynamic random access memory chip through different chip selection signals so as to realize the movement of data from the read operation of the source address dynamic random access memory chip to the write operation of the target address dynamic random access memory chip; and the memory controller is used for controlling the switch array of the data input / output switch circuit so as to establish data paths among different chips.

Description

technical field [0001] This field relates to the communication field, in particular, relates to a dynamic random access memory (DRAM) system communication architecture based on the double rate synchronous dynamic random access memory (DDR) standard. Background technique [0002] With the advent of the era of big data and artificial intelligence, the storage and movement of data has gradually become the bottleneck of existing computing systems. The communication between the memory and the CPU is mainly through a long board-level bus as a medium, which will bring huge delay and energy overhead. In some special scenarios, for example, fork system call (fork system call), mysql (relational database management system) and shell script (script), etc., there are a large number of data copying and initialization clearing operations. [0003] At present, for operations such as data copying, moving, and initialization clearing, such as figure 1 As shown, generally the CPU executes t...

AI Technical Summary

Problems solved by technology

But in this scenario, the CPU does not process the data, it is just a data porter, which seriously wastes the limited board-level bus bandwidth and energy, and occupies CPU resources, aggravating the "memory wall" between the memory and the CPU. "question

Images