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1442 results about "Time windows" patented technology

Parking system path planning method based on dynamic time windows

The invention discloses a parking system path planning method based on dynamic time windows, and belongs to the technical field of path planning. The method is characterized by comprising the following steps: S1, building a work environment model of AGVs in an intelligent garage in a topological method; S2, setting priority for each AGV and each car parking/picking task according to different evaluation criteria; S3, using a Dijkstra algorithm to plan a shortest possible path for an AGV accepting a task; S4, arranging feasible path time windows; S5, designing conflict resolution strategies according to different types of conflicts; and S6, planning a conflict-free optimal path for the AGV using a parking system path planning algorithm based on dynamic time windows. A time-sharing use strategy is used, and the Dijkstra algorithm and a time window method are combined effectively, so that the problem that the existing multi-AGV path planning is of poor flexibility and is prone to deadlock or collision conflict is solved effectively, and a shortest conflict-free optimal path can be planned for an AGV accepting a task. In addition, the overall operation efficiency of an intelligent three-dimensional parking system can be improved effectively, and the car parking/picking waiting time can be reduced for social members.
Owner:JIANGSU MARITIME INST

Techniques for placing applications in heterogeneous virtualized systems while minimizing power and migration cost

N applications are placed on M virtualized servers having power management capability. A time horizon is divided into a plurality of time windows, and, for each given one of the windows, a placement of the N applications is computed, taking into account power cost, migration cost, and performance benefit. The migration cost refers to cost to migrate from a first virtualized server to a second virtualized server for the given one of the windows. The N applications are placed onto the M virtualized servers, for each of the plurality of time windows, in accordance with the placement computed in the computing step for each of the windows. In an alternative aspect, power cost and performance benefit, but not migration cost, are taken into account; there are a plurality of virtual machines; and the computing step includes, for each of the windows, determining a target utilization for each of the servers based on a power model for each given one of the servers; picking a given one of the servers with a least power increase per unit increase in capacity, until capacity has been allocated to fit all the virtual machines; and employing a first fit decreasing bin packing technique to compute placement of the applications on the virtualized servers.
Owner:IBM CORP

Image sensor pixel for global electronic shuttering

A pixel design for CMOS image sensors that has a high frame rate potential and, therefore, provides motion capture capabilities. The pixel is designed for global electronic shuttering so every pixel is exposed simultaneously to images incident upon the pixel array plane. The present invention has the advantages of: (1) Allowing the accommodation of changes in the pixel output groupings for different monochrome output format or CFA patterns with only changes in metal routing layers; (2) allowing true electronic shuttering to image moving scene with all the pixels having the same capture time windows; and (3) providing a symmetric global shutter gate and transfer gate to minimize pixel related fixed pattern noise. The pixel architecture provides for a CMOS based, active pixel image sensor comprising an array of pixels formed in rows and columns, with each of the pixels containing at least one active circuit element. There are a plurality of output channels formed such that each of the output channels are operatively connected to a subset of pixels wherein each of the pixel have an attribute that is the same. The pixel architecture also provides an output gate region and a shutter gate region that are symmetric about the center of the pixel. By arranging the shutter and transfer gates, a symmetric manner about the center of the pixel, a more efficient transfer of electrons to these gates is provided. A Pixel Output Bus structure allows configurable connections to column-wise signal busses that provide parallel output channels.
Owner:OMNIVISION TECH INC
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