34 results about "Memory refresh" patented technology

Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

Techniques for adjusting a frequency at which a memory controller polls a refresh flag are disclosed. Traffic counters are maintained to track traffic to portions of a memory device. A traffic balance is computed using the traffic counters, which indicates a distribution of the traffic to the portions of the memory device. For example, where access operations are performed equally in two halves of a memory bank, the traffic to the memory bank is equally balanced. In memory devices implementing background refresh traffic technology, high traffic balance may indicate that a memory device is likely to be adequately refreshed because opportunities for background refresh operations are evenly distributed. As a result, a memory controller may reduce the frequency at which a refresh flag of the memory is polled when the total traffic exceeds a threshold and when the traffic balance exceeds a threshold.

A storage device may maintain data integrity for data stored on a memory device when the storage device is disconnected from a host for a given period of time. The storage device may include a memory device including blocks for storing data and a connection to an external power source that provides power to the storage device when the storage device is disconnected from the host. The storage device may also include a controller to monitor the health of the blocks on the memory device. The controller may determine a power capability of the external power source and the background operations that may be performed based on the power capability of the external power source and the health of the blocks on the memory device. The controller may refresh the data on the memory device based on the power capability of the external power source.

The invention discloses a memory detection and check method and system based on coding, and the method comprises the steps: setting a dual-refresh constant for each memory region in a memory corresponding to each processor, and each group of dual-refresh constants comprises two refresh constants which are opposite to each other; performing periodic memory refreshing on the memory by using double refreshing constants, wherein the period comprises an odd period and an even period; wherein in the odd period, one refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area, and in the even period, the other refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area; reading back the memory area after the memory is refreshed, and calculating a check word based on data obtained by reading back; and checking the check word obtained by calculation. According to the memory detecting and checking method and system based on coding, the condition that a specific bit in the memory is wrong can be effectively detected, and the reliability and safety of the system are improved.

The embodiment of the invention provides a data persistence method and device, equipment, a medium and a product, and relates to the technical field of data processing.The method comprises the steps that through a state management library of a data persistence system, an application program is initialized to obtain initial configuration data; in response to user operation, triggering a corresponding business process and modifying related data to obtain modified data and a modified state, after the state of the application program is converted into the modified state from the initialized state, screening out a specific state field or module data needing to be encrypted and persistent, and storing the specific state field or module data in a local storage medium after encryption processing. The problem that in the prior art, dynamic data of the application program are only stored in a memory and are prone to being lost after being refreshed or restarted is solved, a user does not need to acquire or process related information again, meanwhile, data safety is guaranteed through encryption processing, and the effect that the application program is rapidly recovered to the modified state after being refreshed or restarted is achieved.

The present invention relates to the field of automobile monitoring technology, and in particular to a wake-up control method for a driving recorder based on a STR mode and a sensor. The method comprises the following steps: obtaining ACC power-off signal data, determining the power supply status based on the ACC power-off signal data, and generating switching instruction data for the system operating mode; analyzing the power consumption state transition of the system-on-chip and image sensor based on the switching instruction data to generate STR mode status data and standby mode status data; analyzing the retention state of the dynamic random access memory based on the STR mode status data, and evaluating the data integrity at the current memory refresh frequency to generate retention feature data; and evaluating the sensor preheating time based on the standby mode status data to obtain sensor rapid activation timing data. By combining the STR mode of the SOC with the standby mode of the sensor, the present invention creates a low-power hardware architecture.

The application provides a vehicle navigation method and device, a vehicle and a readable storage medium. The method comprises the following steps: obtaining an offset and an index value of a road where the vehicle is located from a third-party data terminal; the offset is used to represent the distance between a preset prompt position and an initial position of the vehicle; the initial position of the vehicle is the departure position of the vehicle on the current road; determining the memory refresh number when the third-party data terminal sends the offset according to the offset and the index value; calculating the cumulative offset of the vehicle based on the memory refresh number and the offset; the cumulative offset is the actual distance between the preset prompt position and the initial position of the vehicle; and navigating the vehicle based on the cumulative offset. The application can effectively solve the problem that the offset received by the vehicle cannot be directly applied to vehicle navigation.

A system includes a plurality of memory devices and a processing device (e.g., a controller) operatively coupled to the plurality of memory devices. The processing device is to detect a power-up of the system and determine a read retry trigger rate (TR) for a subset of codewords of the plurality of memory devices during a time interval after initialization of a memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full memory refresh of the plurality of memory devices.

A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.

Aspects of the present disclosure relate to techniques and processes for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refresh. In some aspects, a memory refresh scheduling algorithm may account for memory access batch processing (e.g., read batches, write batches). In some aspects, a refresh scheduling algorithm may schedule more refreshes or prioritize refreshes to occur during write batches to reduce memory read access latency because less refreshes are scheduled during memory read accesses. These techniques may be adapted to reduce write latency.

The present invention provides a memory refresh rate management method, system, storage medium and device, the method comprising: simulating the refresh rate, temperature and capacitance state in combination with the use environment of the memory, and storing a basic model established based on the simulation results in a memory controller; the memory controller obtains the real-time temperature of the memory body, and obtains a real-time function model of the capacitance charge and the charge and discharge time in combination with the basic model; in response to the capacitor being charged after a read and write operation and its charge dropping to a service threshold, the memory is refreshed; the memory controller obtains the memory temperature change and the memory particle access frequency monitored by the monitor; in response to the abnormality of the linear function of the temperature change over time and / or the abnormality of the data access address distribution, the data encryption function is turned on and / or the memory refresh rate is increased. According to the present invention, the problem of frequent memory read and write errors when the temperature and memory self-refresh frequency are not properly matched can be effectively solved, thereby improving the user service quality.

The invention relates to the technical field of network security management, in particular to a computer network security management system and method based on data analysis. The method comprises the following steps: fitting a reference disturbance curve of an inherent disturbance behavior according to network exchange characteristic parameters of a router, and evaluating a forwarding time sequence mismatch degree; performing risk access judgment according to the forwarding time sequence mismatch degree, intelligently evaluating the network security state of the current router, and determining the current security situation level; memory address allocation of the router is updated in real time based on the current security situation level, and a high-risk resource scheduling strategy is obtained; performing network attack chain collaborative plugging based on the current security situation level to form a linkage defense response strategy; and realizing computer network security management according to the high-risk resource scheduling strategy and the linkage defense response strategy. According to the method, physical layer isolation of abnormal traffic of network equipment and self-adaptive network security defense are realized by accurately identifying memory refresh disturbance characteristics and a hotspot access mode.

A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data in a first memory device of a plurality of memory devices. A cached data item on a second memory device of the plurality of memory devices is identified. A valid-to-invalid ratio of the victim MU is compared to a threshold value. In view of comparison, it is determined whether to pad the cached data item with at least a subset of the valid data stored at the victim MU or dummy data. Based on the determination, the cached data item padded with one of at least a subset of the valid data stored at the victim MU or the dummy data is written to a target MU.

In some examples, provided is a method for managing memory refresh operations in a dynamic random access memory, DRAM, bank, the method comprising measuring a leakage current of an electronic device within a DRAM bank, generating, based on the measured leakage current, an oscillating signal using an oscillator, counting a number of cycles of the oscillating signal, comparing the number of cycles of the oscillating signal to a pre-defined threshold value, and, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refreshing the DRAM bank.

An electronic device and a control method for memory refresh operation thereof are provided. The electronic device includes a memory and a controller. The memory includes a plurality of timers, a plurality of buffers and an interrupt signal generator. Each of the buffers is configured to store at least one word line information, and generate a refresh word line information according to a timing result trigger signal of each corresponding timer. The interrupt signal generator generates an interrupt signal corresponding to an auto refresh operation according to the timing result trigger signal, a non-internal self-refresh mode signal and a non-accessing status. The controller receives the interrupt signal and transmits an auto refresh command to the memory according to the interrupt signal to enable the memory to perform the auto refresh operation.

Embodiments of the present application provide a method, apparatus, and memory controller for performing a memory refresh count. The memory refresh count method, applied to a memory controller, comprises: obtaining a target command that affects a self-refresh count; and determining, based on the type of the target command, adjusting a refresh count of a logic block corresponding to the command, wherein the refresh count is stored in a random access memory (RAM), and the logic block is a logical unit within the memory. Some embodiments of the present application can achieve more accurate scheduling of memory refresh commands by identifying commands that affect the refresh count and instantly changing the refresh count, ultimately improving the memory's ability to access data.

A method for flexible memory refresh period control is described. The method includes identifying one or more temperature sensors placed in selected regions of one or more memory dies supported by a system-on-chip (SoC) base die during formation of a memory die stack. The method also includes monitoring temperature sensor values of the one or more temperature sensors during operation of the memory die stack. The method further includes adjusting a memory refresh period control of a region of a memory die from the one or more memory dies when a temperature sensor value of a temperature sensor corresponding to the region is greater than the temperature sensor values based on the monitoring.

The application relates to the field of speech recognition, and discloses a speech recognition system for robots based on deep learning, which comprises a voice input module for collecting and denoising voice signals; a feature extraction module for converting the voice signals into a mel spectrum graph or MFCC features; a deep learning model module based on a Transformer-XL architecture, which processes input features through a multi-head self-attention mechanism and captures context information in combination with a cross-time step memory unit; an optimal memory management module for dynamically planning and optimizing a memory refresh strategy and dynamically adjusting a memory state; an adaptive attention mechanism module for adaptively adjusting the weight of an attention head based on a Lagrange multiplier method; and an output module for converting model output into text or robot control instructions. The method improves the accuracy and robustness of speech recognition, enhances the processing capacity of the system in long conversations and complex contexts, and is suitable for application scenarios such as robot control and home management.

Limiting a leakage current of a memory device is provided. A sensing current that is a representative of a leakage current of a memory cell array of a memory device is generated. A reference current having a preset value is generated. The sensing current is compared with the reference current. An enable signal is generated based on the comparison. A bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal.

The invention provides an operation method of a memory, a dynamic random access memory and a memory system, and relates to the technical field of semiconductor chips. The method comprises the steps of determining a target storage array in response to a storage array activation signal, and performing a refresh operation on the target storage array in response to a refresh signal. The invention aims to improve the problem of high power consumption in a memory refreshing process.

The invention provides an adaptive memory refreshing method, a memory controller and a storage medium. The self-adaptive memory refreshing method comprises the following steps: caching a refreshing request of a memory in a first cache queue, and caching a data access request of the memory in a second cache queue; wherein one refresh cycle comprises a plurality of refresh requests, each refresh request is a request for performing refresh operation on a part of rows of the memory, and rows to be refreshed by different refresh requests in the same refresh cycle are completely different; the data access of the memory comprises: reading or writing of the memory; obtaining a state signal of the first cache queue, a state signal of the second cache queue and a signal indicating whether the currently executed memory operation task is completed or not, and generating a new memory operation task according to the scheduling priorities of the refresh request of the memory and the data access request of the memory based on the three signals; wherein the memory operation comprises a refreshing operation of the memory or a data access operation of the memory.

This application provides a memory refresh method, apparatus, electronic device, and storage medium, relating to the field of computer technology. The method includes: determining a first set of memory pages based on modification operations on memory pages of non-volatile memory, the first set of memory pages including at least one address range of memory pages; determining a second set of memory pages from the first set of memory pages based on a write-back triggering mechanism, the second set of memory pages including a target address range to be refreshed, the write-back triggering mechanism including a trigger period, a trigger condition, or a computer system power failure event; determining the content to be refreshed from a cache based on the target address range, and refreshing the content to be refreshed from the cache to the corresponding physical address segment of the non-volatile memory. This application can ensure that the latest version of the content is stored in the non-volatile memory even in the event of a power failure.

A memory idle-time refresh method and system that resists the accumulation of single-particle upset effects. When the processor accesses the memory sparsely or idle, a read operation is initiated to refresh the data in the memory, and the data that has experienced a single-particle upset is checked and corrected. The error site is recorded and an interrupt is sent to the processor. The error address, the read source data, and the check code are stored in the corresponding register to be read and judged by the processor. The refresh process is executed by the programmable memory autonomous access component. During the refresh period, the processor can execute other operation programs except memory access. After the refresh process is completed, the processor can access the memory normally. The present invention can autonomously complete the memory refresh task without occupying the processor's computing resources when the processor accesses the memory sparsely or idle, thereby preventing the accumulation of errors caused by single-particle upsets in memory in space applications, and preventing single-bit errors from becoming double-bit errors or multi-bit errors.

The invention relates to the technical field of automobile monitoring, in particular to an automobile data recorder awakening control method based on an STR mode and a sensor. The method comprises the following steps: acquiring ACC power-off signal data, judging a power supply state through the ACC power-off signal data, and generating switching instruction data of a system working mode; analyzing power consumption state conversion for the system-on-chip and the image sensor based on the switching instruction data, and generating STR mode state data and standby mode state data; analyzing the retention state of the dynamic random access memory according to the STR mode state data, evaluating the data integrity under the current memory refresh frequency, and generating retention characteristic data; and evaluating the preheating time of the sensor based on the standby mode state data to obtain quick activation time sequence data of the sensor. The STR mode of the SOC and the standby mode of the sensor are combined, and a low-power-consumption hardware architecture is created.

Techniques and mechanisms for selectively throttling operation of circuitry, wherein said throttling is based on a threshold rate at which a memory is to be refreshed. In an embodiment, a power management unit (PMU) accommodates coupling to receive an identifier of a first refresh rate which has been requested with the random access memory (RAM) device. The PMU provides functionality to calculate a difference between a threshold maximum refresh rate and the first refresh rate. Based on the calculated difference, a throttle action is identified, and one or more control signals are generated to throttle operation of circuitry which is thermally coupled with the RAM device. In another embodiment, the RAM device continues to be refreshed at the first refresh rate during and / or after the throttling of the circuitry.

A method includes obtaining target information of a rank, and then determining a memory refresh mode of the rank from a plurality of memory refresh modes based on the target information. The target information indicates a quantity of commands or traffic of the rank, and power consumption of the rank varies in the plurality of memory refresh modes.

This application relates to memory refresh operations using reduced power. The technology described herein relates to protecting at least a portion of data stored in a memory array. A method can include detecting an invalid memory access request based at least in part on a secret key and an identifier, and preventing unauthorized access of a memory array by stopping internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

The invention relates to a memory refreshing method and device, electronic equipment, a storage medium and a computer program product, and the method comprises the steps: generating a memory refreshing request corresponding to a target memory according to a memory refreshing interval corresponding to the target memory; under the condition that the memory refresh request backlog number is larger than a first threshold value, one memory refresh request is selected to be determined as a target memory refresh request, and the memory refresh request backlog number is used for indicating the total number of memory refresh requests which are not executed currently; according to the working state and the load state of each non-refreshed memory bank in the target memory under the current refresh round, the refresh priority of each non-refreshed memory bank is determined; and determining the non-refreshed memory bank with the highest refresh priority as a target non-refreshed memory bank, and sending a target memory refresh request to the target non-refreshed memory bank. According to the embodiment of the invention, the conflict probability between the target non-refreshed memory bank executing memory refreshing and high load can be reduced, and the memory performance is further obviously improved.

Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

A method for flexible memory refresh period control is described. The method includes identifying one or more temperature sensors placed in selected regions of one or more memory dies supported by a system-on-chip (SoC) base die during formation of a memory die stack. The method also includes monitoring temperature sensor values of the one or more temperature sensors during operation of the memory die stack. The method further includes adjusting a memory refresh period control of a region of a memory die from the one or more memory dies when a temperature sensor value of a temperature sensor corresponding to the region is greater than the temperature sensor values based on the monitoring.