14 results about "Memory refresh" patented technology

Techniques for adjusting a frequency at which a memory controller polls a refresh flag are disclosed. Traffic counters are maintained to track traffic to portions of a memory device. A traffic balance is computed using the traffic counters, which indicates a distribution of the traffic to the portions of the memory device. For example, where access operations are performed equally in two halves of a memory bank, the traffic to the memory bank is equally balanced. In memory devices implementing background refresh traffic technology, high traffic balance may indicate that a memory device is likely to be adequately refreshed because opportunities for background refresh operations are evenly distributed. As a result, a memory controller may reduce the frequency at which a refresh flag of the memory is polled when the total traffic exceeds a threshold and when the traffic balance exceeds a threshold.

A storage device may maintain data integrity for data stored on a memory device when the storage device is disconnected from a host for a given period of time. The storage device may include a memory device including blocks for storing data and a connection to an external power source that provides power to the storage device when the storage device is disconnected from the host. The storage device may also include a controller to monitor the health of the blocks on the memory device. The controller may determine a power capability of the external power source and the background operations that may be performed based on the power capability of the external power source and the health of the blocks on the memory device. The controller may refresh the data on the memory device based on the power capability of the external power source.

The invention discloses a memory detection and check method and system based on coding, and the method comprises the steps: setting a dual-refresh constant for each memory region in a memory corresponding to each processor, and each group of dual-refresh constants comprises two refresh constants which are opposite to each other; performing periodic memory refreshing on the memory by using double refreshing constants, wherein the period comprises an odd period and an even period; wherein in the odd period, one refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area, and in the even period, the other refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area; reading back the memory area after the memory is refreshed, and calculating a check word based on data obtained by reading back; and checking the check word obtained by calculation. According to the memory detecting and checking method and system based on coding, the condition that a specific bit in the memory is wrong can be effectively detected, and the reliability and safety of the system are improved.

The embodiment of the invention provides a data persistence method and device, equipment, a medium and a product, and relates to the technical field of data processing.The method comprises the steps that through a state management library of a data persistence system, an application program is initialized to obtain initial configuration data; in response to user operation, triggering a corresponding business process and modifying related data to obtain modified data and a modified state, after the state of the application program is converted into the modified state from the initialized state, screening out a specific state field or module data needing to be encrypted and persistent, and storing the specific state field or module data in a local storage medium after encryption processing. The problem that in the prior art, dynamic data of the application program are only stored in a memory and are prone to being lost after being refreshed or restarted is solved, a user does not need to acquire or process related information again, meanwhile, data safety is guaranteed through encryption processing, and the effect that the application program is rapidly recovered to the modified state after being refreshed or restarted is achieved.

A system includes a plurality of memory devices and a processing device (e.g., a controller) operatively coupled to the plurality of memory devices. The processing device is to detect a power-up of the system and determine a read retry trigger rate (TR) for a subset of codewords of the plurality of memory devices during a time interval after initialization of a memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full memory refresh of the plurality of memory devices.

A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.

In some examples, provided is a method for managing memory refresh operations in a dynamic random access memory, DRAM, bank, the method comprising measuring a leakage current of an electronic device within a DRAM bank, generating, based on the measured leakage current, an oscillating signal using an oscillator, counting a number of cycles of the oscillating signal, comparing the number of cycles of the oscillating signal to a pre-defined threshold value, and, in response to determining that the number of cycles of the oscillating signal exceeds the pre-defined threshold value, refreshing the DRAM bank.

A method for flexible memory refresh period control is described. The method includes identifying one or more temperature sensors placed in selected regions of one or more memory dies supported by a system-on-chip (SoC) base die during formation of a memory die stack. The method also includes monitoring temperature sensor values of the one or more temperature sensors during operation of the memory die stack. The method further includes adjusting a memory refresh period control of a region of a memory die from the one or more memory dies when a temperature sensor value of a temperature sensor corresponding to the region is greater than the temperature sensor values based on the monitoring.

Limiting a leakage current of a memory device is provided. A sensing current that is a representative of a leakage current of a memory cell array of a memory device is generated. A reference current having a preset value is generated. The sensing current is compared with the reference current. An enable signal is generated based on the comparison. A bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal.

This application provides a memory refresh method, apparatus, electronic device, and storage medium, relating to the field of computer technology. The method includes: determining a first set of memory pages based on modification operations on memory pages of non-volatile memory, the first set of memory pages including at least one address range of memory pages; determining a second set of memory pages from the first set of memory pages based on a write-back triggering mechanism, the second set of memory pages including a target address range to be refreshed, the write-back triggering mechanism including a trigger period, a trigger condition, or a computer system power failure event; determining the content to be refreshed from a cache based on the target address range, and refreshing the content to be refreshed from the cache to the corresponding physical address segment of the non-volatile memory. This application can ensure that the latest version of the content is stored in the non-volatile memory even in the event of a power failure.

This application relates to memory refresh operations using reduced power. The technology described herein relates to protecting at least a portion of data stored in a memory array. A method can include detecting an invalid memory access request based at least in part on a secret key and an identifier, and preventing unauthorized access of a memory array by stopping internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

A method for flexible memory refresh period control is described. The method includes identifying one or more temperature sensors placed in selected regions of one or more memory dies supported by a system-on-chip (SoC) base die during formation of a memory die stack. The method also includes monitoring temperature sensor values of the one or more temperature sensors during operation of the memory die stack. The method further includes adjusting a memory refresh period control of a region of a memory die from the one or more memory dies when a temperature sensor value of a temperature sensor corresponding to the region is greater than the temperature sensor values based on the monitoring.

Various embodiments include methods and devices for implementing scaling of a memory frequency configuration by a computing device. Embodiments include comparing at least a memory refresh rate, a memory size, at least one use case bandwidth for transmission between a memory and a system on chip (SoC), and a use case latency for transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored memory refresh rate, at least one stored memory latency, at least one stored memory refresh rate, at least one stored memory latency, and at least one stored memory refresh rate. Comparing the bandwidth of the at least one stored use case sent between the memory and the SoC with the delay of the at least one stored use case sent between the memory and the SoC; selecting a memory frequency based on all results of these comparisons; and configuring the memory for the memory frequency. Some embodiments may include issuing an alert indicating a change in use to enable memory to implement use case parameters.

Various embodiments include a method for implementing a multi-bank memory refresh command on a memory device. The memory controller may select a number of memory banks to be refreshed in a refresh cycle, select a first memory bank to be refreshed, and transmit a multi-bank memory refresh command encoding the number of memory banks to be refreshed and the first memory bank to the memory device. The memory device may identify a multi-bank memory refresh command based on signals received over a number of clock cycles, decode the command to identify a number of memory banks to be refreshed and a first memory bank to be refreshed, and then refreshing the identified number of memory banks starting from the identified first memory bank.