Dynamic memory refreshing method and refreshing controller

Abstract

The invention discloses a dynamic memory refreshing method and a refreshing controller, and belongs to the technical field of semiconductor memories. According to the dynamic memory refreshing method, based on a grain unit memory, by using a manner than the grain memory unit has two groups of mutually independent word lines and bit lines, read/write operation of external access is completed within an upper-half period of a clock, and refreshing read/refreshing write operation is completed within a lower-half period of the clock. According to the dynamic memory refreshing method, a refreshing request signal and a refreshing state signal are generated according to a refreshing period of the gain unit, a line number of a memory Bank and a clock period; control signals of corresponding refreshing read and refreshing write operations are generated according to a refreshing state to control refreshing read and refreshing write operations and external read/external write operation to be performed in parallel. According to the dynamic memory refreshing method, the confliction between a refreshing operation and the external access is eliminated, so that the memory can be accessed completely randomly in real time.

Description

technical field [0001] The invention belongs to the technical field of semiconductor memory, and more specifically relates to a dynamic memory refresh method and a refresh controller. Background technique [0002] Data in dynamic memory (DRAM) is typically stored in capacitors in dynamic memory cells. Due to the leakage current of the MOS transistor in the dynamic memory unit, the charge stored on the capacitor will disappear, resulting in data loss. Therefore, in order to prevent data loss in the dynamic storage unit, the dynamic storage unit needs to be refreshed periodically. Each row of memory cells in the DRAM array needs to be refreshed once in a specific cycle. The refresh cycle of DRAM depends on factors such as memory cells and manufacturing processes. The current DRAM has the following typical refresh technologies: [0003] (1) A burst refresh (Burst Refresh) technology, when a refresh request signal is received, all rows in the memory Bank are sequentially ref...

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Problems solved by technology

[0008] Aiming at the above defects or improvement needs of the prior art, the present invention is based on the gain unit embedded memory, utilizes the non-destructive read operation characteristics of the gain unit, and the mutually independent read and write word line and read and write bit line structures to provide a dynamic The purpose of the memory refr

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