A dynamic memory refresh method and refresh controller

A technology of dynamic memory and controller, which is applied in the direction of static memory, digital memory information, information storage, etc. It can solve the problems that external access cannot be performed randomly and in real time, internal refresh conflicts, etc., and achieve the effect of short access cycle and improved access rate

Inactive Publication Date: 2017-10-03
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
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Problems solved by technology

[0008] Aiming at the above defects or improvement needs of the prior art, the present invention is based on the gain unit embedded memory, utilizes the non-destructive read operation characteristics of the gain unit, and the mutually independent read and write word line and read and write bit line structures to provide a dynamic The purpose of the memory refresh method and the refresh controller is to enable the external access to read and write normally while the internal refresh of the memory bank is being performed, thereby solving the problem that external access and internal refresh conflict, resulting in external access not being able to be performed randomly and in real time , and improve access efficiency

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  • A dynamic memory refresh method and refresh controller
  • A dynamic memory refresh method and refresh controller
  • A dynamic memory refresh method and refresh controller

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[0031] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0032] The present invention provides an implicit refresh method, based on the gain unit memory, using the gain memory unit to have two sets of mutually independent word lines and bit lines to divide the refresh operation into four sub-stages: idle, refresh read, refresh cache control and refresh write back , divided into two consecutive clock cycles to complete. Divide the external read access...

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Abstract

The invention discloses a dynamic memory refresh method and a refresh controller, belonging to the technical field of semiconductor memory. The present invention is based on the gain unit memory, utilizes the gain storage unit to have two sets of mutually independent word lines and bit lines, completes the read / write operation of external access in the first half cycle of the clock, and completes the refresh read / refresh write operation in the second half cycle of the clock operate. The present invention generates a refresh request signal and a refresh state signal according to the refresh synchronization of the gain unit, the row number of the storage bank, and the clock cycle; generates a corresponding refresh read and refresh write operation control signal according to the refresh state to control the refresh read and refresh write operations with the external Read / external write operations are performed in parallel. The invention eliminates the conflict between refresh operation and external access, and enables the memory to be accessed completely randomly and in real time.

Description

technical field [0001] The invention belongs to the technical field of semiconductor memory, and more specifically relates to a dynamic memory refresh method and a refresh controller. Background technique [0002] Data in dynamic memory (DRAM) is typically stored in capacitors in dynamic memory cells. Due to the leakage current of the MOS transistor in the dynamic memory unit, the charge stored on the capacitor will disappear, resulting in data loss. Therefore, in order to prevent data loss in the dynamic storage unit, the dynamic storage unit needs to be refreshed periodically. Each row of memory cells in the DRAM array needs to be refreshed once in a specific cycle. The refresh cycle of DRAM depends on factors such as memory cells and manufacturing processes. The current DRAM has the following typical refresh technologies: [0003] (1) A burst refresh (Burst Refresh) technology, when a refresh request signal is received, all rows in the memory Bank are sequentially ref...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/406
Inventor 桑红石王文张天序梁巢兵高英华石志伟何宏张鹏剑
Owner HUAZHONG UNIV OF SCI & TECH
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