Memory refresh device and memory refresh method

Abstract

A memory refresh device comprises an ordinary patrol control unit (24) for controlling an ordinary patrol operation in which a memory (11) is patrolled, an additional patrol control unit (25) for, when an error of the memory (11) is detected in the ordinary patrol operation, controlling an additional patrol operation in which an error generating portion in the memory (11) is patrolled, a measuring unit (15) for, when an error is detected in the additional patrol operation, measuring information on the error in the error generating portion as error frequency, and a refresh period adjusting unit (26) for adjusting a refresh period according to the error frequency measured by the measuring unit (15). Thus, the optimization of the refresh period is efficiently performed according to the state of the generation of the error in the memory.

Description

technical field [0001] The present invention relates to a technique for performing memory refresh in conjunction with a refresh cycle of the memory. Background technique [0002] Due to the high performance of computers in recent years, the loss of time and power consumption when refreshing memories such as DRAM (Dynamic Random Access Memory) cannot be ignored. Therefore, the refresh cycle is controlled so that the memory refresh is performed at a long cycle when errors (data errors) are unlikely to occur, and is shortened when operating conditions are severe and errors are likely to occur. [0003] Figure 18 It is a diagram schematically showing an example of a conventional operation method for controlling a memory refresh cycle. [0004] In the existing memory refresh cycle control method, for example, as Figure 18 As shown, using the memory refresh circuit 90, the memory refresh cycle is controlled while the memory 91 is monitored for errors. For example, the Figure ...

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Problems solved by technology

[0016] However, in the above-mentioned conventional operation method for controlling the memory refresh cycle, the above-mentioned Patent Document 1 and the above-mentioned Patent Document 2, it is always necessary to perform error detection on the entire memory.

Therefore, there is a problem that it takes time to detect a locally generated error when only a part of the address in the memory has an error, and the responsiveness decreases when the operating environment of the system changes temporarily.

[0017] In particular, the above-mentioned Patent Document 1 and the above-mentioned Patent Document 2 are technologies based on the premise of the control of the memory in the standby mode. Therefore, the refresh cycle can be changed only in the standby mode, but cannot be changed dynamically during normal operation. Changing the refresh cycle does not allow optimization of the refresh cycle in accordance with the occurrence of errors in the memory.

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