The invention discloses an SRAM (static random access memory)-oriented anti-SEU (single-event upset) error accumulation controller and method. The controller comprises a register group, a memory access information generation circuit, a memory access state transfer control circuit, a check code decoding module, an rdata register, a multiplexer, an EDAC (error detection and correction) encoding module, a pdata register and a wdata register. When a processor performs other operations other than access of a main memory, a memory controller of the processor autonomously performs traversal read, check and write-back operations on all storage units, the traversal refresh operation takes a most basic SRAM storage unit as a unit; when the refresh operation of one storage unit is completed, the refresh address is progressively increased, a state machine is controlled to be back to an idle state, and whether the processor has memory access operation or not is detected again. According to the controller and the method, disclosed by the invention, idle time of a system is fully utilized, and SEU error accumulation of the SRAM storage units can be avoided on the basis of not affecting the performance of the processor.