SRAM (static random access memory)-oriented anti-SEU (single-event upset) error accumulation controller and method

Abstract

The invention discloses an SRAM (static random access memory)-oriented anti-SEU (single-event upset) error accumulation controller and method. The controller comprises a register group, a memory access information generation circuit, a memory access state transfer control circuit, a check code decoding module, an rdata register, a multiplexer, an EDAC (error detection and correction) encoding module, a pdata register and a wdata register. When a processor performs other operations other than access of a main memory, a memory controller of the processor autonomously performs traversal read, check and write-back operations on all storage units, the traversal refresh operation takes a most basic SRAM storage unit as a unit; when the refresh operation of one storage unit is completed, the refresh address is progressively increased, a state machine is controlled to be back to an idle state, and whether the processor has memory access operation or not is detected again. According to the controller and the method, disclosed by the invention, idle time of a system is fully utilized, and SEU error accumulation of the SRAM storage units can be avoided on the basis of not affecting the performance of the processor.

Description

technical field [0001] The patent of the invention belongs to the technical field of fault tolerance, and relates to a controller and method for SRAM-oriented anti-SEU error accumulation. Background technique [0002] SRAM (Static Random Access Memory), that is, static random access memory, has the following main advantages: (1) It can keep data without refreshing; (2) The read and write access cycle is short. Under the same conditions, SRAM has higher performance and reliability than DRAM, and is widely used in electronic systems with high real-time requirements such as aerospace and aviation. [0003] With the advancement of SRAM manufacturing process and the reduction of core voltage, the possibility of SRAM single-event upset (Single-event Upset, SEU) in harsh environments increases rapidly. The current engineering practice proves that SEU is a type of soft error with the highest probability of occurrence in the space environment, and SEU only causes one Bit to flip in ...

AI Technical Summary

Problems solved by technology

However, the probabilistic refresh technology can only perform refresh operations on memory cells that have read operations, and cannot refresh SRAM memory cells that have not been read for a long time, so some SRAM memory cells (SRAM memory cells that do not perform read operations) cannot be avoided. SEU errors keep accumulating

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