Memory interface for systems with multiple processors and one memory system

Abstract

Memory interface for multi-CPU system provides predefined time slots in which each CPU may access an external memory. The time slot assigned to each CPU may be defined according to the expected memory requirements of the CPU. In this way, each CPU is guaranteed to have a certain amount of dedicated bandwidth to the external memory. The predefined time slots also allow the latency of the system to be known, which is useful for real-time oriented applications. Moreover, each CPU may use its own clock during its allotted time slot to control the external memory, thus accommodating various clock domains in the system. Memory refresh and data protection functions are also provided. This Abstract is provided to comply with rules requiring an Abstract that allows a searcher or other reader to quickly ascertain subject matter of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This Application claims priority from, and hereby incorporates by reference, U.S. Provisional Application Nos. 60 / 509,503, filed Oct. 8, 2003; 60 / 510,074, filed Oct. 9, 2003; and 60 / 530,960, filed Dec. 19, 2003, all bearing the title “High Performance and Reliability Memory Interface for Systems with Multiple CPUs and One Memory.”BACKGROUND [0002] 1. Technical Field [0003] The present invention relates to memory systems and, in particular, to an interface for a memory system that is accessible by multiple processors. [0004] 2. History of Related Art [0005] A control processor (CPU) requires memory in order to operate. The memory may be on the same integrated circuit or “chip” with the CPU, as in the case of a digital application specific integrated circuit (ASIC), or it may be located externally. On-chip memory has the advantage of being faster than external memory, but is more expensive and not very scalable. Thus, the amount of on-chi...

AI Technical Summary

Benefits of technology

[0008] A memory interface provides predefined time slots in which each of a plurality of CPUs may access the external memory. A time slot assigned to each CPU may be defined according to the expected memory requirements of the CPU. Each CPU is guaranteed to have a certain amount of dedicated bandwidth to the external memory. The predefined time slots allow the latency of the system to be known, which is useful for real-time oriented applications. Moreover, each CPU may use its own clock during its allotted time slot to control the external memory, thus accommodating various clock domains in the system. Memory refresh and data protection functions are also provided.

[0009] In general, in one aspect, the invention is directed to a method of granting access to a single external memory from multiple control processors. The method comprises the steps of defining a first time slot and a second time slot, granting access to the external memory to a first control processor during the first predefined time slot, and granting access to the external memory to a second control processor during the second predefined time slot.

[0010] In general, in one aspect, the invention is directed to a memory interface for allowing multiple control processors to access a single external memory. The memory interface comprises a first control processor, a second control processor, and an arbiter inter-operably connected to and synchronized with one of the first and second control processors. The arbiter is configured to grant access to the external memory to the first control processor during a first predefined time slot and grant access to the external memory to the second control processor during the second predefined time slot.

[0011] It should be emphasized that the term comprises / comprising, when used in this specification, is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

Problems solved by technology

On-chip memory has the advantage of being faster than external memory, but is more expensive and not very scalable.

Thus, the amount of on-chip memory in most digital ASICs is relatively small.

Since only one CPU may control the external memory at a time, a number of challenges are placed on the design of the memory interface.

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