The invention relates to the technical field of
chip optimization, in particular to a
chip performance optimization method and device,
electronic equipment and a storage medium, and the method comprises the steps: planning input data and weight data through employing a three-dimensional MAC array additionally arranged in a target
chip, and obtaining a distribution scheme; according to the distribution scheme and the trapezoidal
shift register array, carrying out time-sharing loading on the input data, and shifting the input data subjected to time-sharing loading to obtain an input
data stream; and according to the input
data stream and the weight data, performing
convolution calculation on each multiplier-
adder unit in the three-dimensional MAC array in sequence to obtain an optimized pipeline calculation result of the target chip. According to the invention, the computing architecture based on the three-dimensional MAC array is optimized, the proportion of read-write operation is reduced, and the overall computing efficiency of the chip is improved; by optimizing the
data processing flow, it is ensured that the calculation process can be continuously carried out, the proportion of calculation duration is increased, and time
delay caused by read-write operation is shortened.