147 results about "Execution cycle" patented technology

The invention relates to the technical field of artificial intelligence, in particular to a cloud edge collaborative production manufacturing management system based on artificial intelligence, which comprises a task scheduling optimization module, a resource scheduling and load balancing module, a production efficiency evaluation module, a dynamic load adjustment module and a fault tracing analysis module. According to the invention, by accurately analyzing the task dependency relationship, optimizing the task scheduling strategy and improving the response sequence and delay control of task execution, the processing bottleneck problem caused by data transmission delay is avoided, the task execution period is flexibly adjusted, the high-frequency tasks in the production process are effectively managed, and the load unevenness caused by fluctuation is reduced; the method can accurately identify and regulate the production bottleneck, improve the adaptive capability of the production process, accurately identify the potential fault source, shorten the fault diagnosis time, reduce the complexity, more rapidly position the problem, improve the stability, efficiency and fault tolerance of the production system, and integrally enhance the self-optimization capability of the production system.

The invention discloses a GPU computing power resource scheduling method and device based on load awareness and a medium, and relates to the technical field of computing power scheduling. The method comprises the steps that according to the video memory capacity and the number of calculation cores of the GPU, the video memory capacity is divided into a plurality of continuous fragments, the calculation cores are divided into a plurality of logic calculation groups, and sub-resource units are obtained; recording occupation states and load indexes of the sub-resource units in real time to obtain a resource pool; analyzing a job submitted by a user, and collecting an execution period of a kernel function, a video memory access mode and an instruction pipeline blocking rate when the job runs; and on the basis of a reinforcement learning algorithm, predicting a resource demand inflection point of the job according to the load fingerprint model, performing hierarchical scheduling on the sub-resource units based on virtualization isolation and multi-dimensional resource quantitative evaluation, and generating a preemptive allocation strategy of the sub-resource units. According to the method, efficient utilization and secure sharing of GPU resources are realized through collaborative design of dynamic granularity segmentation, load aware scheduling and hardware-level security isolation.

The embodiment of the invention relates to the field of artificial intelligence, and discloses an agent collaborative execution system based on a task dialogue link, and electronic equipment. An agent management station; the task scheduling and execution module is used for generating a corresponding dialogue node when task scheduling is triggered each time in the process of executing the periodic task by the intelligent agent, and a plurality of dialogue nodes corresponding to the periodic task form a dialogue link according to a time sequence; the agent access and collaboration interface module is used for realizing interaction between the agent collaboration execution system and the agent; the agent workbench comprises a task management and execution viewing module which is used for responding to the periodic task execution viewing request and displaying the execution process of the periodic task in the form of a dialogue link. A dialogue link is formed by orderly connecting dialogue nodes, so that the execution process of the periodic task has a uniform and displayable data organization form, and backtracking, auditing and multiplexing of the execution process are facilitated.

The invention discloses a coroutine scheduling method, device, system and equipment, a storage medium and a product, and relates to the technical field of task scheduling, a multi-priority queue group is used for storing a first coroutine task to be executed in a corresponding scheduling domain, and a storage module is used for storing a second coroutine task periodically executed in a corresponding scheduling domain; the execution cycle of the first coroutine task is smaller than that of the second coroutine task. And when the expired second coroutine task exists in the storage module, mounting the expired second coroutine task to the multi-priority queue group. The situation that the first coroutine task with the low priority cannot be executed due to the fact that the second coroutine task does not reach the execution time is effectively avoided. And the coroutine tasks are obtained and executed from the multi-priority queue group according to the priority sequence, so that the tasks with high priorities are ensured to preferentially obtain execution resources. According to the running state and the load state of each scheduling domain, task migration of each scheduling domain is carried out, and the resource utilization rate is optimized.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention provides an automobile electronic control unit fuzzy testing method based on partial code coverage rate feedback and a computer, and belongs to the technical field of automobile electronic control unit code testing. The computer performs static analysis on source codes of the automobile electronic control unit, identifies inevitable execution blocks and conditional execution blocks, performs selective instrumentation on the conditional execution blocks, and inserts coverage rate recording instructions of the conditional execution blocks. And the computer source code is loaded into the automobile electronic control unit, and a test input signal is generated through the fuzzy test engine and is injected into the automobile electronic control unit. In the process of executing the program by the automobile electronic control unit, recording the coverage condition of the condition execution block to a bitmap in the memory; the computer reads the coverage rate data of the condition execution block through the debugger every time a complete execution cycle is completed; and the fuzzy test engine adjusts the input generation strategy according to the coverage rate data feedback of the condition execution block and tests again. According to the method, the automobile electronic control unit source code fuzzy test coverage condition is efficiently collected.

The invention provides refrigeration equipment, relates to the technical field of household appliances, and is used for realizing operation of an artificial intelligence algorithm while a refrigeration function of a refrigerator is not influenced under the condition that resources of a main control chip of the refrigerator are limited. The refrigeration equipment comprises a box body, a refrigeration system, a heater, a memory and a controller, wherein a target model is deployed in the memory; the controller is configured to split a target algorithm task corresponding to the target model into a plurality of algorithm sub-tasks; executing at least one algorithm sub-task in the plurality of algorithm sub-tasks in the residual execution duration of at least one execution cycle of the plurality of execution cycles; wherein the remaining execution duration is the remaining duration after all the core tasks are executed in each execution period, and the core tasks are used for achieving normal operation of the refrigeration equipment; and running the plurality of execution cycles until the plurality of algorithm sub-tasks end running, and obtaining a running result of the target model.

The invention provides an experimental task scheduling method and device for an intelligent laboratory, and is applied to a server in a laboratory system of a target laboratory, and the method comprises the steps: obtaining an experimental task pool; determining a priority weight according to the task sensitivity level and the predicted time consumption of each experimental task; determining equipment execution information according to each task type; determining a task execution queue corresponding to each preset reference experimental device in the target laboratory according to the device execution information and the priority weight corresponding to the plurality of experimental tasks; and converting the task execution queue into an operation instruction sequence to control the experiment robot in the target laboratory to execute the experiment task through the reference experiment equipment. Thus, the server achieves the process from experimental task scheduling to robot driving equipment execution based on the equipment execution information and the priority weight, an end-to-end automatic process is constructed, the intellectualization of a target laboratory is improved, the equipment resource utilization rate is effectively increased, and the task execution period is shortened.

The invention relates to the field of chemiluminescence immunity analyzers, and discloses a high-speed full-automatic chemiluminescence immunity analyzer multi-module parallel motion control method, which comprises the following steps: in a current execution period, pre-calculating all secondary function module action instruction sets of a next period based on real-time position information of a reaction cup and test sample parameters; according to a pre-generated instruction set, coordinating parallel actions of multiple modules through a preposition and subsequent dependency relationship, and driving a hardware execution unit to complete sample processing; and synchronizing the reaction cup position data and the test step state in real time, and switching to a next period instruction set when the period is ended. According to the method, the problems of time sequence conflict and resource contention of multi-module cooperative control are solved, the parallel efficiency of the detection process and the fault-tolerant capability of the system are improved, and the method is suitable for a high-throughput chemiluminescence immunoassay scene.

The invention discloses an embedded software architecture method applied to a digital power supply. The embedded software architecture method comprises the following steps: S1, timed scheduling basis: generating a tick mark; a hardware timer of the MCU / DSP is taken as a core, and a tick mark with a fixed period is generated and is taken as a time reference of task scheduling of the whole system; s2, task cycle division: according to product requirements, disassembling functions into different tasks, and allocating corresponding execution cycles; s3, a time-sharing scheduling mechanism: only executing a task of a current time slice in each ticking cycle; s4, simulating operation system logic: realizing multi-task processing through'round-robin '; s5, core interruption: a loop control algorithm; pWM period interruption or ADC sampling interruption is used for triggering, the priority is the highest, and only loop control is executed. According to the invention, the problems that the real-time performance is low and the response time is uncontrollable and long when a general embedded operating system is applied to digital power supply control software are solved.

A simulation method for simulating a target circuit design comprising a plurality of micro-architecture hyper-parameters. The method comprises decompiling a binary code to obtain a control flow graph comprising multiple basic blocks (101, 120); generating multiple basic block chains, BBCs, based on the plurality of basic blocks taking account of the micro-architecture hyper-parameters (102, 130); performing, for each BBC, cycle-accurate simulation (104, 150) based on the determined context (103, 140), to obtain cycle count information (150); storing the cycle count information into a database (105, 160); performing instruction-accurate simulation (106) using the binary code, to obtain instruction traces indicating executed BBC; retrieving, for each executed BBC, corresponding cycle count information from the database (107); and determining overall cycle count information of the binary code on the target circuit design by accumulating the retrieved cycle count information of the executed BBCs (108). In this way, a fast and accurate simulation can be achieved.

This invention discloses a task scheduling method and system based on an ITSM platform, belonging to the field of IT service management technology. The method includes the following steps: acquiring an available execution node cluster; collecting task execution records of nodes within a second scheduling set to generate a true performance baseline; performing periodic node rotation operations between the first and second scheduling sets based on historical execution data and the true performance baseline; calibrating the historical execution data of the first scheduling set; monitoring the real-time load distribution of the first scheduling set to trigger emergency node rotation operations; performing emergency node rotation operations and resetting historical data for nodes that have undergone rotation; and updating the initial node quantity ratio. This invention solves the problems of hotspot solidification, self-fulfilling oracle, and cluster resource utilization imbalance caused by historical affinity bias in existing technologies by dividing execution nodes into a first scheduling set and a second scheduling set.

A simulation method for simulating a target circuit design comprising a plurality of micro-architecture hyper-parameters. The method comprises decompiling a binary code to obtain a control flow graph comprising multiple basic blocks (101, 120); generating multiple basic block chains, BBCs, based on the plurality of basic blocks taking account of the micro-architecture hyper-parameters (102, 130); performing, for each BBC, cycle-accurate simulation (104, 150) based on the determined context (103, 140), to obtain cycle count information (150); storing the cycle count information into a database (105, 160); performing instruction-accurate simulation (106) using the binary code, to obtain instruction traces indicating executed BBC; retrieving, for each executed BBC, corresponding cycle count information from the database (107); and determining overall cycle count information of the binary code on the target circuit design by accumulating the retrieved cycle count information of the executed BBCs (108). In this way, a fast and accurate simulation can be achieved.

A task execution system and method of a vehicle operation system according to a preferred embodiment of the present application, wherein the task execution system of the vehicle operation system includes a task information extraction section that extracts task information related to an event signal received from an application from a preset event chain table, a task execution cycle setting section that sets a task execution cycle using the extracted task information, a task execution section that executes one task of a plurality of tasks according to the task execution cycle, and a waiting time providing section that provides a task waiting time to the task execution section to wait for a next task execution if the one task execution is completed.

This invention relates to the field of intelligent manufacturing and industrial automation technology, specifically to an intelligent order scheduling and material management system for a milling and turning workshop. It includes a task parsing module, a feature mapping module, a state acquisition module, a potential field construction module, a scheduling calculation module, and a feedback execution module. The system receives task drawing data and bill of materials data, extracts geometric feature bounding dimension data and machining tool vector sequence data, and tensors and encodes them. It collects the current tool library configuration status parameters of the target machining equipment and the physical attribute parameters of work-in-process, constructs a continuous potential energy field distribution matrix, and dynamically refreshes it. It calculates the potential energy gradient descent direction of the multidimensional machining feature tensor flow, generates a task queue of associated paths and a theoretically estimated execution cycle time sequence, issues CNC machining task plans and automated guided vehicle (AGV) allocation instructions, and feeds back the actual cycle deviation correction value for closed-loop updates. This invention makes the scheduling results closer to the actual executable state of the workshop.

The application belongs to the technical field of automatic control, and specifically discloses a uranium enrichment auxiliary process air conditioning box system APC and RTO online cooperation method, which comprises the following steps: step 1, APC algorithm modeling; step 2, designing a penalty function and an execution cycle T of APC optimization APC ; step 3, designing an RTO optimization penalty function, a weight coefficient and an RTO cycle; and step 4, initializing APC and RTO optimization parameters and starting a continuous cycle operation. According to the method, numerical model and penalty function are constructed, optimization control is realized based on the prediction of the trend of the cascade hall in the future time interval, thus, the disturbance can be prevented and inhibited in a forward-looking manner, the temperature control stability and precision are ensured, and the air conditioning equipment of the auxiliary process system can be operated in an unattended, efficient and energy-saving manner.

Embodiments of the present application provide a message processing method and device, applied in the field of data processing, comprising: obtaining a transaction message, the transaction message being sent by a first transaction system and / or a second transaction system, the transaction message containing an execution path of the message; storing the transaction message in an initial directory, periodically executing a control script to read the transaction message in the initial directory through an execution period set by a timing task, and putting the read transaction message into a target directory; and processing the transaction message in the target directory according to the execution path in the transaction message. The control of the to-and-fro message script is added on the message processing system, and the transmission of the to-and-fro message is controlled through the timing task in the control of the to-and-fro message script.

A scheduling device that schedules functions executed by a plurality of in-vehicle control devices capable of communicating with each other via a communication bus, the scheduling device being provided with: an acquisition unit that acquires first information for determining a first execution start timing and a first execution cycle, and second information for determining a second execution start timing and a second execution cycle; the second information is used to determine a first execution start timing at which a first function executed by the first in-vehicle control device and the second in-vehicle control device is started, and a second execution cycle at which the first function is executed, and a second execution start timing at which the first function is executed by the first in-vehicle control device and the second in-vehicle control device. The second execution start timing is a timing at which a second function executed by the first in-vehicle control device and a third in-vehicle control device is started, and the second execution period is a period at which the second function is executed; and a determination unit configured to determine whether the first information and the second information are different from each other. The first execution start timing, the first execution cycle, the second execution start timing, and the second execution cycle at which the total power consumption of the first, second, and third in-vehicle control devices is minimized are determined.

The invention discloses an SIMD instruction arrangement method based on an RISC-V architecture, and belongs to the field of processor instruction arrangement. The method comprises the following steps: identifying and analyzing an SIMD applicable part in a calculation process as a calculation task for SIMD optimization; designing a basic code template according to the calculation task, and abstractly expressing the calculation task; mapping the operation in the basic code to an SIMD calculation structure; designing an SIMD (Single Instruction Multiple Data) instruction according to the vector extension characteristic of the RISC-V architecture; the SIMD instruction sequence is rearranged, so that the instructions of the loop body are expanded, the same instructions are executed in a centralized mode, the idle period between the instructions is shortened, and the parallelism degree and throughput of instruction execution are improved. According to the method, the execution cycles of all types of instructions are shortened, so that the overall computing performance is greatly improved, the energy consumption is reduced, the resource utilization rate is improved, and the GPU is more efficient when processing large-scale parallel computing tasks.

Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

The invention provides a performance analysis system of a processor and a performance analysis method of the processor, the performance analysis system of the processor comprises a configuration module, a determination module, an obtaining module and a calculation module, the configuration module is used for configuring a function part and a constraint relation corresponding to the processor; the determination module is used for determining a time point constraint of each assembly instruction according to each assembly instruction in the assembly code use case, a functional part corresponding to the processor, a constraint relationship and a scheduling strategy; the obtaining module obtains the total execution cycle number of the assembly code case according to the time point constraint of each assembly instruction and the instruction sequence of each assembly instruction; and the calculation module is used for calculating the number of assembly instructions executed by the processor in each clock period according to the total execution period number of the assembly code use case and the total number of the assembly instructions. According to the performance analysis system of the processor and the performance analysis method of the processor provided by the embodiment of the invention, the performance analysis efficiency of the processor is improved.

The invention relates to a data loading method and device, electronic equipment, a storage medium and a computer program product. The method comprises the steps of determining a configuration file required by a photographing function in response to a starting request for the photographing function; performing preloading processing on the configuration file to obtain preloading information; based on the first execution cycle and the second execution cycle, caching each configuration parameter included in the configuration file to a corresponding storage space; based on the execution time of the configuration parameters in each storage space, determining a loading sequence of each storage space; according to the loading sequence of the storage spaces corresponding to all the configuration files, the configuration parameters in the storage spaces are loaded in sequence. According to the embodiment of the invention, the configuration parameters can be cached to different storage spaces according to the execution cycle of the configuration parameters, the loading sequence of each storage space is determined accordingly, the configuration parameters in the different storage spaces are loaded in a time-sharing manner according to the loading sequence, and the data load and the memory occupation when the camera is started can be optimized.

The invention provides a data acquisition and pushing system and method, electronic equipment and a storage medium. The system comprises a display layer, a scheduling layer, a splitting layer, an execution layer and a storage layer, the display layer is used for acquiring connection information and task configuration files of multiple databases; the scheduling layer is used for scheduling a current collection task related to a plurality of databases to be collected according to the execution period; the splitting layer is used for splitting the current collection task into a plurality of sub-tasks in one-to-one correspondence with a plurality of databases to be collected, and pushing the plurality of sub-tasks to the message queue; the execution layer is used for remotely connecting a plurality of to-be-collected databases according to the connection information, traversing and executing each target data query script associated with a subtask corresponding to each to-be-collected database to obtain current collected data, and pushing the current collected data to a target end in response to the situation that the current collected data meets a batch pushing condition in the execution process; the storage layer is used for recording a corresponding execution result in response to the completion of execution of the current collection task.

The invention relates to an equipment data interaction method and system, automation equipment and a medium, and the equipment data interaction method applied to data sending end equipment comprises the steps: determining a storage address of target data needing to be interacted after a demand for providing interaction data for data receiving end equipment is generated; and reading the target data according to the storage address, writing the target data into a write-out buffer area of the target data, and sending the target data in the write-out buffer area to a reading buffer area of the data receiving end equipment by a data refreshing thread of which the execution period is smaller than the minimum task period, therefore, the data receiving end device can read the target data when the target data of the data sending end device needs to be read in the task period. According to the method, data sharing at any moment in a period is realized, logic abnormal values and real-time values can be positioned more accurately, finer running state information can be acquired to realize more accurate control and quicker response, and the flexibility and expandability of the system are improved.

The invention relates to a motor control method and device, control equipment and a storage medium, and the method comprises the steps: obtaining the motion state of each output shaft in a first group of output shafts of a multi-shaft motor; for each output shaft, determining a target loop execution period of a plurality of control loops of the output shaft according to the motion state of the output shaft; adjusting an original loop execution period of the output shaft according to the target loop execution period; and controlling the execution of the plurality of control loops according to the target loop execution period. Through a loop execution period dynamic optimization strategy, the execution periods of the speed ring and the position ring are adaptively adjusted according to the motion state of each axis, and the calculation load is reduced on the premise of ensuring the control performance.

Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

The present application discloses a coroutine scheduling method, apparatus, system, equipment, storage medium and product, which relates to the field of task scheduling technology, wherein a multi-priority queue group is used to store the first coroutine task to be executed in its corresponding scheduling domain, and a storage module is used to store the second coroutine task that is executed regularly in its corresponding scheduling domain; the execution period of the first coroutine task is less than the execution period of the second coroutine task. When there is an expired second coroutine task in the storage module, the expired second coroutine task is mounted to the multi-priority queue group. This effectively avoids the situation where the second coroutine task has not reached the execution time, resulting in the first coroutine task with a low priority being unable to be executed. The coroutine tasks are obtained and executed from the multi-priority queue group in order of priority, ensuring that tasks with a high priority obtain execution resources first. Task migration of each scheduling domain is performed according to the operating status and load status of each scheduling domain, thereby optimizing resource utilization.

The application discloses a data processing method and device, and relates to the technical field of computers. A specific implementation manner of the method comprises the following steps: determining whether a first type of task execution cycle is reached; if yes, generating an election instruction corresponding to the first type of task, and performing election according to the election instruction; and if elected as a leader node corresponding to the first type of task, executing the first type of task. The implementation manner splits the main function of the system into the first type of task and a second type of task, executes the first type of task through dynamic election, realizes a decentralized architecture, and does not have a central node in the cluster, so that the failure of any node can be taken over by other nodes in the cluster, and the size of the cluster can be dynamically horizontally expanded. On the other hand, all the nodes in the cluster actively acquire the second type of task, replace the mode of being forced to accept tasks in a mainstream architecture, and realize automatic balanced distribution of tasks according to the processing capacity of the nodes.

The application discloses a dynamic taint analysis method and system for firmware full-system simulation, and the method comprises the following steps: S1, after starting the taint tracking function, when receiving the data to be analyzed, the physical memory address of the current data in the virtual machine is found, and the specified part is marked as taint in the shadow memory; S2, during the execution cycle of the taint marked data to be analyzed, the TCG instruction of the client instruction disassembled is instrumented, and the preset taint propagation instruction is inserted before each instruction to manipulate the propagation of taint information, so that the TCG instruction after being instrumented realizes the flow of taint information during the interpretation execution process; S3, the taint detection module detects the taint information in real time, and when it is detected that the register or shadow memory storing the key information is marked as taint, the taint propagation is ended and the pollution state information is output. The application can track taint information in real time and accurately during firmware full-system simulation.

The invention discloses an embedded GPU (Graphic Processing Unit) computing resource allocation method and device. The method comprises the following steps: receiving a task execution request sent by a CPU (Central Processing Unit); under the condition that the target interface is determined to be the interface related to resource use, determining the number of target tokens required by the task in the current task execution period according to the interface identifier and the GPU occupancy rate; the current token number in the container is obtained, and when it is determined that the current token number is larger than or equal to the target token number, a kernel task is issued to the target interface; and if it is determined that the number of the current tokens is smaller than the number of the target tokens, waiting for a next token updating period, and after the number of the tokens is supplemented to the number of the target tokens, issuing a kernel task to the target interface. According to the scheme, the use of the computing resources of each task is controlled through a token mechanism, the resource allocation is accurately carried out in a fine-grained manner, the resource allocation can be dynamically adjusted, and the performance interference among the tasks is reduced.