56 results about "Execution cycle" patented technology

The embodiment of the invention relates to the field of artificial intelligence, and discloses an agent collaborative execution system based on a task dialogue link, and electronic equipment. An agent management station; the task scheduling and execution module is used for generating a corresponding dialogue node when task scheduling is triggered each time in the process of executing the periodic task by the intelligent agent, and a plurality of dialogue nodes corresponding to the periodic task form a dialogue link according to a time sequence; the agent access and collaboration interface module is used for realizing interaction between the agent collaboration execution system and the agent; the agent workbench comprises a task management and execution viewing module which is used for responding to the periodic task execution viewing request and displaying the execution process of the periodic task in the form of a dialogue link. A dialogue link is formed by orderly connecting dialogue nodes, so that the execution process of the periodic task has a uniform and displayable data organization form, and backtracking, auditing and multiplexing of the execution process are facilitated.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

This invention discloses a task scheduling method and system based on an ITSM platform, belonging to the field of IT service management technology. The method includes the following steps: acquiring an available execution node cluster; collecting task execution records of nodes within a second scheduling set to generate a true performance baseline; performing periodic node rotation operations between the first and second scheduling sets based on historical execution data and the true performance baseline; calibrating the historical execution data of the first scheduling set; monitoring the real-time load distribution of the first scheduling set to trigger emergency node rotation operations; performing emergency node rotation operations and resetting historical data for nodes that have undergone rotation; and updating the initial node quantity ratio. This invention solves the problems of hotspot solidification, self-fulfilling oracle, and cluster resource utilization imbalance caused by historical affinity bias in existing technologies by dividing execution nodes into a first scheduling set and a second scheduling set.

A task execution system and method of a vehicle operation system according to a preferred embodiment of the present application, wherein the task execution system of the vehicle operation system includes a task information extraction section that extracts task information related to an event signal received from an application from a preset event chain table, a task execution cycle setting section that sets a task execution cycle using the extracted task information, a task execution section that executes one task of a plurality of tasks according to the task execution cycle, and a waiting time providing section that provides a task waiting time to the task execution section to wait for a next task execution if the one task execution is completed.

This invention relates to the field of intelligent manufacturing and industrial automation technology, specifically to an intelligent order scheduling and material management system for a milling and turning workshop. It includes a task parsing module, a feature mapping module, a state acquisition module, a potential field construction module, a scheduling calculation module, and a feedback execution module. The system receives task drawing data and bill of materials data, extracts geometric feature bounding dimension data and machining tool vector sequence data, and tensors and encodes them. It collects the current tool library configuration status parameters of the target machining equipment and the physical attribute parameters of work-in-process, constructs a continuous potential energy field distribution matrix, and dynamically refreshes it. It calculates the potential energy gradient descent direction of the multidimensional machining feature tensor flow, generates a task queue of associated paths and a theoretically estimated execution cycle time sequence, issues CNC machining task plans and automated guided vehicle (AGV) allocation instructions, and feeds back the actual cycle deviation correction value for closed-loop updates. This invention makes the scheduling results closer to the actual executable state of the workshop.

Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

The invention relates to an equipment data interaction method and system, automation equipment and a medium, and the equipment data interaction method applied to data sending end equipment comprises the steps: determining a storage address of target data needing to be interacted after a demand for providing interaction data for data receiving end equipment is generated; and reading the target data according to the storage address, writing the target data into a write-out buffer area of the target data, and sending the target data in the write-out buffer area to a reading buffer area of the data receiving end equipment by a data refreshing thread of which the execution period is smaller than the minimum task period, therefore, the data receiving end device can read the target data when the target data of the data sending end device needs to be read in the task period. According to the method, data sharing at any moment in a period is realized, logic abnormal values and real-time values can be positioned more accurately, finer running state information can be acquired to realize more accurate control and quicker response, and the flexibility and expandability of the system are improved.

The application discloses a data processing method and device, and relates to the technical field of computers. A specific implementation manner of the method comprises the following steps: determining whether a first type of task execution cycle is reached; if yes, generating an election instruction corresponding to the first type of task, and performing election according to the election instruction; and if elected as a leader node corresponding to the first type of task, executing the first type of task. The implementation manner splits the main function of the system into the first type of task and a second type of task, executes the first type of task through dynamic election, realizes a decentralized architecture, and does not have a central node in the cluster, so that the failure of any node can be taken over by other nodes in the cluster, and the size of the cluster can be dynamically horizontally expanded. On the other hand, all the nodes in the cluster actively acquire the second type of task, replace the mode of being forced to accept tasks in a mainstream architecture, and realize automatic balanced distribution of tasks according to the processing capacity of the nodes.

The application discloses a dynamic taint analysis method and system for firmware full-system simulation, and the method comprises the following steps: S1, after starting the taint tracking function, when receiving the data to be analyzed, the physical memory address of the current data in the virtual machine is found, and the specified part is marked as taint in the shadow memory; S2, during the execution cycle of the taint marked data to be analyzed, the TCG instruction of the client instruction disassembled is instrumented, and the preset taint propagation instruction is inserted before each instruction to manipulate the propagation of taint information, so that the TCG instruction after being instrumented realizes the flow of taint information during the interpretation execution process; S3, the taint detection module detects the taint information in real time, and when it is detected that the register or shadow memory storing the key information is marked as taint, the taint propagation is ended and the pollution state information is output. The application can track taint information in real time and accurately during firmware full-system simulation.

This invention relates to the field of chip design technology, and in particular to a method, device, and storage medium for obtaining correction coefficients for instruction execution efficiency. The invention obtains test cases used to test the efficiency of various instructions in the pre-silicon stage. Before silicon, the test cases are tested in a verification environment based on a simulator. After the test cases are executed, the estimated and actual execution efficiency values ​​of each instruction are obtained. The estimated value is obtained by reading the values ​​of an instruction counter used to record the instruction execution cycle and a state counter used to record the clock cycle in which the processor core is in operation. The actual value is obtained based on the instruction execution cycle and the actual data in the waveform information generated by the simulator. Based on the estimated and actual values ​​of each instruction, a correction coefficient for each instruction is obtained, solving the problem of the inability to accurately obtain the execution efficiency of instructions during post-silicon testing.

The invention relates to the technical field of large-scale concurrent data processing and information interaction, and discloses a data processing method for massive interaction behaviors, which comprises the following steps: acquiring an input stream representing a learning behavior business processing interaction request sequence in a distributed interaction behavior processing system, and extracting time sequence characteristics; an atomic-scale null operation instruction pair is injected into the scheduling unit, and kernel scheduling resistance is determined according to the deviation between an actual value and a standard value of an instruction execution period; the method comprises the following steps of: calculating a density momentum value of an input flow, executing weighted compensation on a preset threshold value by utilizing kernel scheduling resistance, generating a dynamic judgment threshold value for defining a processing strategy switching boundary, and controlling a system to switch between a low-power-consumption mode and a high-flux mode. Response delay burrs under high-concurrency loads are eliminated, deep coupling of a processing mode and an operation environment is achieved, and the processing efficiency of behavior interaction data of an online education system is improved.

An energy management device and a method of processing multiple virtual power plant (VPP) events, by the energy management device, are provided. The method includes determining whether to store a new event obtained from a VPP server, in a processing queue, determining whether a first execution period, which is an execution period of the newly stored first event according to the determining, overlaps with a second execution period, which is an execution period of a second event stored before the first event, and establishing an execution plan for the first event and the second event in response to the determining that the first execution period overlaps with the second execution period.

The application discloses a kind of supply chain data quality automatic check and closed loop management method and system, it is related to supply chain digital technology field, including the following steps: the supply chain authority source list obtained is input into the preset check rule set, according to rule check result extraction problem field set;Problem field set is injected into DCAN responsibility mapping mechanism, and the ability matrix is output through the pre-constructed multi-modal responsibility intelligent agent, and the responsibility proportion weight of responsibility subject is calculated based on ability matrix;The responsibility proportion weight is input into responsibility allocation decision model, and the allocation responsibility of corresponding responsibility subject is output;According to allocation responsibility, dispatch problem rectification task to corresponding responsibility subject;If it is detected that rectification fails, then extract rectification failure field set, and according to the preset responsibility transmission path, rectification failure field set is transmitted to secondary responsibility subject, and the problem is solved until execution cycle is performed.This application is used to solve the problem that data responsibility attribution is not clear, rectification task is dispatched, and there is lack of tracking after rectification process is broken.

The invention relates to the technical field of computational graph optimization, in particular to a computational graph optimization method, system and device supporting large model reasoning, and the method comprises the steps: monitoring the communication frequency and data transmission quantity of any two nodes in a computational graph in all model reasoning in each execution cycle, and the bottleneck bandwidth and round-trip delay of the two nodes, determining the affinity of any two nodes; generating a plurality of initial allocation schemes, and determining the maximum execution time of the allocation schemes; determining the cross-device communication time of the allocation scheme, constructing a target function in combination with the maximum execution time, and obtaining an optimal allocation scheme; and determining the cumulative saving delay and the migration cost overhead of each execution cycle, comparing the cumulative saving delay and the migration cost overhead with the cumulative saving delay, and evaluating the migration of the nodes in the computational graph to optimize the computational graph. According to the method, reasoning delay can be reduced, resource waste and performance reduction caused by blind migration can be avoided, and distribution of the computational graph can be comprehensively and dynamically optimized.

The embodiment of the invention provides a communication control method, a communication control system and a rocket. The method comprises the following steps: setting a reference period of a message corresponding to each instruction in advance: setting a scheduling control period for checking all messages; setting a reference period of a message corresponding to each instruction based on the number of the instructions and the scheduling control period, determining an execution period of the message of the 1553B bus based on the maximum reference period, and dispersing the reference periods of different messages in different scheduling control periods in the same execution period; checking the message in each scheduling control period through the bus controller; after the message is checked, the 1553B bus is scheduled through the bus controller in the message execution window so that the 1553B bus can be adopted for communication and transmission of the message; the purpose of dispersing the message execution windows is achieved by dispersing the message reference period, and message transmission overlapping is not caused, so that message transmission congestion is not caused.

The invention discloses an operation and maintenance monitoring method and system based on an operation and maintenance model and automatic script driving. According to the method, firstly, an operation and maintenance model can be customized by constructing configuration attributes and performance attributes, and then different operation and maintenance instances are generated according to different configuration attributes; secondly, compiling a custom script, selecting an issuing server, customizing an execution cycle, executing parameters and binding an operation and maintenance instance to issue the script; the script executor performs script execution according to information such as a script execution period and parameters, and injects an execution result into a performance attribute corresponding to the operation and maintenance instance so as to play a role in periodically collecting an operation and maintenance instance index; the script issuing execution process and the execution result injection process are mutually independent, script execution and operation and maintenance instance maintenance can be decoupled, and the problems that due to the fact that configuration attributes and performance attributes of common operation and maintenance instances are changed, an index collection method is changed, and a monitoring program is frequently modified are solved.

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processor. The apparatus may obtain an indication of a scene including a plurality of primitives, wherein each of the plurality of primitives includes a set of vertices. The apparatus may also determine position data for each vertex in the set of vertices for each of the plurality of primitives. Further, the apparatus store, or refrain from storing, the position data for each vertex in the set of vertices for each of the plurality of primitives based on an execution cycle associated with the position data.

The disclosure provides a single-sensor-based multitask execution method and device, electronic equipment and storage medium. The method comprises: generating a first type of hardware interrupt at intervals of an execution cycle of a task that does not need to meet safety standards; if it is detected that the first type of hardware interrupt is generated, executing a first preset program of a task that needs to meet safety standards, including reading an electrical signal collected by a single sensor, and writing the analyzed electrical signal into a shared storage area; and based on the analyzed data, continuing to execute the task that needs to meet safety standards under the condition that the execution cycle is met, and triggering the generation of a second type of hardware interrupt regardless of whether the execution is continued; if it is detected that the second type of hardware interrupt is generated, executing a second preset program of a task that does not need to meet safety standards, including accessing the shared storage area, obtaining the analyzed data, and continuing to execute the task that does not need to meet safety standards based on the analyzed data. Accordingly, both software isolation and functional safety are met, and the cost of the sensor is reduced.

A closed dialog-based input system (200) for generating a binding operating model with a fixed execution reference, comprising: a stepwise dialog acquisition unit (210) with a receiving interface for successive dialog-based inputs via any physical or logical input channel, wherein separate dialog stages are storable and referenceable; a dialog state fixing unit (220) for fixing an operational state after each dialog stage; and a dialog conversion unit (230) with an extraction unit for a predefined set of operational parameters from each fixed dialog stage, as well as a generation unit for referential operational parameters in the absence of explicit input of certain parameters.- a unit for generating a fixed dialogic and execution-related reference as well as a unique identifier of an independent execution cycle (240), - a unit for structural dialogic validation (250) with a validation structure for ensuring the reference consistency of all dialogic stages and operational parameters within the execution cycle, - a dialogic execution lock (260), and - a stepwise dialog and execution protocol (270), characterized in that the input system (200) is configured such that - after each dialogic stage, a fixed operational state data record is generated and stored in a reference-bound manner, and - the system architecture technically blocks a transition to a subsequent dialogic stage as well as the transfer of operational parameters or the generation of operational outputs before all operational parameters are extracted or generated, fixed,bound to the fixed execution reference, structurally validated and fixed in a final dialog and execution protocol (270) with a single unchanging reference.

This invention provides a task scheduling method and apparatus. The method includes: arranging all tasks in a task pool from high to low execution priority to obtain a task arrangement; determining the cyclic execution cycle of each task based on its task attributes; cyclically checking the tasks in the task arrangement based on the interrupt service cycle; when a target task in the task arrangement reaches its cyclic execution cycle, writing the target task into a task execution request and exiting the current loop; executing the target task based on the task execution request, and continuing to cyclically check the tasks in the task arrangement. The task scheduling method and apparatus provided by this invention, based on task priority, cyclically checks the tasks in the task pool to ensure the real-time execution of each task and maximize the utilization of system resources. After determining the target task to be executed, the current loop is exited, ensuring that the highest priority task is always executed sequentially.

The invention discloses a real-time abnormal monitoring local automatic recovery method and device, and the method comprises the steps: collecting behavior data in each interruption execution period through injecting monitoring logic, and comparing the behavior data with a baseline model in real time; the sub-health state of an interrupt service program is identified before abnormal triggering of processor hardware and even before obvious deterioration of system scheduling; by performing grade evaluation on the abnormality, recovery actions with different granularities can be adopted according to the severity and the influence range of the abnormality; by continuously monitoring and analyzing the operation behavior of the common interrupt service program, the abnormal trend can be identified in the normal operation stage of the system, and grading and local automatic recovery are implemented according to the abnormal grade, so that the overall restart probability of the system is reduced, and the reliability and the real-time performance of the system are improved.

The invention discloses a service digital processing method based on WBS and a storage medium, and relates to the technical field of information technology fusion. The method comprises the following steps: determining a processing dimension of an initial WBS template based on a business process; determining a service execution period and milestone nodes of the initial WBS template according to the processing dimension; building a service role team of the initial WBS template according to the processing dimension; deconstructing the business process based on a preset decomposition method to obtain a decomposition structure of the initial WBS template; obtaining a service architecture network diagram of the initial WBS template by linking a service unit; carrying out attribute configuration on the service unit and carrying out role allocation on the packet to obtain a target WBS template; and checking the accuracy of the target WBS template, and processing the business process according to the target WBS template. The technical problems that the information transmission efficiency of a traditional business process is low and business experience cannot be reused in the prior art are solved.

The invention relates to a pipeline tight coupling hardware-in-loop verification method, device and equipment and a medium, and the method comprises the steps that an RTL coprocessor recognizes to-be-executed arithmetic logic according to an instruction type identifier, and executes corresponding operation based on a first source operand and a second source operand to generate an operation result, recording an actual execution cycle number corresponding to the instruction type identifier through a cycle counter, and marking as a time sequence violation if the total execution cycle number of the instruction type identifier reaches or exceeds a theoretical execution cycle in combination with a pseudo-random number generated by a 16-bit linear feedback shift register; the RTL coprocessor returns the operation result and the total execution cycle number to the RI SCV-VP virtual prototype, in the write-back stage, the operation result is written back to the target register according to the target register identification operation result, and an advent () function of the assembly line time sequence model is called to verify the returned total execution cycle number so as to update the total cycle number of the system. According to the method, the simulation speed is remarkably improved, and a large amount of hardware resource consumption is not additionally increased.

The application relates to a task scheduling method and device of an embedded system. The method comprises the following steps: obtaining task parameters of all tasks from a task list; determining first execution time of each task on a time axis according to staggered execution time; determining candidate tasks to be executed in each scheduling period according to an execution period and the first execution time; sorting the candidate tasks according to execution priority to generate a sorted task execution sequence in each scheduling period; and scheduling and executing the tasks in the sequence according to the task execution sequence. The method can effectively improve stability and accuracy of task execution timing, guarantee real-time performance of key tasks, and reduce resource competition among multiple tasks.

The invention provides a data processing method, device and system, electronic equipment and a computer storage medium, and relates to the technical field of artificial intelligence and the like. According to the specific implementation scheme, a cue word asset library is connected; receiving and analyzing a workflow definition file written by a user to obtain a step sequence comprising a plurality of steps, the steps comprising reference information for pointing to a target cue word asset in a cue word asset library; an execution context penetrating through the execution cycle is generated, all the steps in the step sequence are executed in sequence, and for all the steps, a cue word template of target cue word assets is obtained from a cue word asset library based on reference information included in the steps; based on input data corresponding to the step in the execution context, performing parameter filling on the cue word template to generate a target cue word; based on the target cue word, interacting with the large language model to obtain an output result of the step; and writing the output result into the execution context.

The present disclosure provides a navigation acceleration processor and a system on chip based on RISC-V extension instructions, which comprises a fetch module, a decoding module, an execution module, a memory access module, a write back module and a controller. The processor core of the present disclosure is extended on the basis of the RISC-V instruction set, and special extension instructions are designed for the common operations in navigation digital signal processing, which effectively reduces the number of instructions required to complete the corresponding operations, thereby improving the operation efficiency and shortening the calculation time. At the same time, further cooperate with the improved multiplication operation unit and division operation unit, shorten the execution period of multiplication and division, improve the energy efficiency ratio, realize the improvement of the operation speed of the processor, and meet the navigation demand.

The present application provides a kind of responsiveness analysis device capable of efficiently confirming the responsiveness of API.Responsiveness analysis device has: execution history acquisition unit, which acquires history information related to API;First decision unit, which determines the execution cycle and processing time of the API corresponding to newly added application;Second decision unit, which determines the execution start time and processing time of the API corresponding to existing application based on the history information acquired by the execution history acquisition unit;And responsiveness analysis unit, which analyzes the responsiveness of the API based on the execution cycle and processing time of the API corresponding to the newly added application and the execution start time and processing time of the API corresponding to the existing application.

The invention provides a high-speed filter stick forming equipment online marking method based on a dynamic window trigger, which comprises the following steps of: accessing an encoder signal of filter stick forming equipment, calculating the minimum detectable pulse number according to the maximum speed and the program execution period of the filter stick forming equipment, and performing pulse compensation; generating a dynamic window trigger with a predetermined total number of output pulses; defining a dynamic window trigger structural body, recording a current encoder pulse position as a starting point when a filter stick type signal rising edge is detected, and dynamically generating a trigger window; meanwhile, an integer type annular queue array with the length of P is defined, an initial pointer cardinal number Base is set, and cyclic updating is carried out according to Base = (Base + 1) mod P when each filter stick is shifted; whether filter stick mark management is executed or not is judged; after enumeration type driven filter stick mark management is carried out, dynamically triggered key tasks are deployed to a real-time task core in a TwinCAT3 software platform, and non-real-time tasks are distributed to a low-priority task core.

The invention discloses a message sending method and device, a storage medium and a computer program product, and relates to the technical field of communication, and the message sending method comprises the steps: determining a message sending period of a plurality of messages of a target vehicle; the priority of the multiple messages is determined according to the multiple message sending periods, the sending time of each message in the multiple messages for sending a first frame of message is determined according to the multiple message sending periods, and the priority is used for indicating the sending sequence of the multiple messages in the same execution period; sending a first frame message of the plurality of messages according to the plurality of sending times, and sending an update frame message of each message in the plurality of messages in a plurality of message sending periods according to the plurality of priorities and an execution period, the execution period being determined according to the plurality of message sending periods, and sending the update frame message of each message in the plurality of message sending periods according to the plurality of priorities. Each message in the plurality of messages comprises a plurality of frames of messages.

This application provides a method and system for incremental hot patching of server hardware firmware vulnerabilities, relating to the field of server hardware firmware repair technology. This application identifies abnormal function nodes with abnormal power consumption by acquiring the operating status data of multiple functional modules; then, based on these nodes, it dynamically adjusts the power state of specific modules and collects power consumption change data when the power supply changes; next, it associates this data with the execution cycle of specific module functions to establish a mapping relationship between function calls and power consumption modes to mark functions to be repaired; subsequently, it generates corresponding hot patch function code and stores it in the system's secure memory area; finally, when a specific module meets low-power conditions, it switches the execution flow of the function to be repaired to the hot patch code through function jump redirection, completing the incremental hot patching of vulnerabilities. This method can accurately identify abnormal functions in server hardware firmware and generate hot patches, and switch the execution flow when a specific module is at low power consumption, thus achieving incremental hot patching of firmware vulnerabilities.