This invention discloses an atomic operation aggregation acceleration method based on RISC-V architecture. The method includes the following steps: extending the execution
semantics of RISC-V atomic operation instructions to introduce an atomic operation aggregation execution mode; introducing an atomic operation aggregation
coprocessor in the processor; when the processor core executes an atomic operation instruction using the aggregation execution mode, it sends an atomic operation request to the atomic operation aggregation
coprocessor; the atomic operation aggregation
coprocessor receives atomic operation requests from multiple concurrent execution contexts and associates the requests with the corresponding aggregators; the aggregator internally accumulates the operands of the
atomic operations and maintains the state information of the current aggregation batch; when a preset aggregation batch
commit condition is met, an aggregation
commit operation is triggered, and an atomic write-back operation is performed on the target
memory address; after the aggregation
commit is completed, the state of the current aggregation batch is reset, and the next aggregation batch is initialized. The purpose of this invention is to address the problems of severe
cache consistency contention,
high memory access pressure, and increased
energy consumption caused by multiple threads frequently performing atomic read-modify-write operations on the same
memory address when multiple processor cores concurrently execute
atomic operations. By introducing an atomic operation aggregation execution mechanism in the RISC-V architecture, the
linearization point of
atomic operations is moved forward to the atomic operation aggregation coprocessor, realizing the merging and batch submission of multiple atomic operation requests, thereby significantly reducing the number of atomic accesses to the target memory, improving
system throughput performance, and reducing memory access
power consumption.