478results about How to "High error rate" patented technology

Route selection through a wireless mesh network between a source node and a destination node is based on minimizing generated interference in order to increase the capacity of the network. An interference energy associated with transmitting a packet over each hop in multiple routes from the source node to the destination node is determined. The interference energy for each hop is combined to generate a combined interference energy for each route. One of the routes is selected based on the combined interference energy determined for each route.

Devices, methods and computer readable mediums storing a program causing a computer to execute a process for interacting with targets on a display, particularly in regards to devices utilizing a multi-touch display that are driven by gestures. The use of such devices, methods, and computer readable mediums storing a program allows the user to interact with devices through the use of multi-touch displays.

In a disk drive that performs perpendicular magnetic recording, the read / write channel has a sync mark generator. The sync mark generator generates a second sync mark before the read / write channel operates to write data on a disk. The second sync mark has a bit pattern including a series of bits representing positive polarity and a series of bits representing negative polarity. The series of bits, which is longer than the other, has a bit length that is at least 50% but less than 85% of the total bit length of the second sync mark.

Techniques for reducing peak-to-average power in multicarrier transmitters employ peak cancellation with subcarriers that are impaired by existing channel conditions. The use of Carrier Interferometry (CI) coding further improves the effectiveness of peak reduction. CI coding can also be impressed onto pulse sequences in the time domain, which enhances spectral selection and facilitates peak-power control.

Provided is a magnetic tape, which comprises, on a nonmagnetic support, a nonmagnetic layer comprising nonmagnetic powder and binder, and on the nonmagnetic layer, a magnetic layer comprising ferromagnetic powder and binder; wherein at least the magnetic layer comprises one or more components selected from the group consisting of a fatty acid and a fatty acid amide; a quantity of components selected from the group consisting of a fatty acid and a fatty acid amide per unit area of the magnetic tape among components that are extracted from a surface on the magnetic layer side of the magnetic tape is less than or equal to 15.0 mg / m2, and a concentration of carbon, C, that is obtained by X-ray photoelectron spectroscopy conducted at a photoelectron take-off angle of 10 degrees on the surface on the magnetic layer side of the magnetic tape is greater than or equal to 50 atom %.

To store an input string of M N-tuples of bits, a substitution transformation is selected in accordance with the input string and is applied to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the memory selectively programs each of M or more cells to a respective one of 2N states. A mapping that maps the binary numbers in [0,2N−1] into respective states is selected in accordance with the input string and is used to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.

The magnetic tape has a magnetic layer containing ferromagnetic powder and binder on the surface on one side of a nonmagnetic support and has a backcoat layer containing nonmagnetic powder and binder on the surface on the other side of the nonmagnetic support, wherein the backcoat layer is less than or equal to 0.30 μm in thickness; and the logarithmic decrement as determined by a pendulum viscoelasticity test on the surface on the backcoat layer side of the magnetic tape is less than or equal to 0.060.

An integrated circuit includes a plurality of processing stages each including processing logic 1014 , a non-delayed signal-capture element 1016 , a delayed signal-capture element 1018 and a comparator 1024 . The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014 . An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024 . The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improvements are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.