226 results about "Zero error" patented technology

The invention relates to systems and methods of measuring low liquid flow rates. The system provides a controller, flow system components, and one or more load cells coupled to a collection vessel. The collection vessel includes a weir that serves as a passage to allow liquid to rise within the weir until the liquid overflows the weir. After the liquid supplied passes a hydraulic stabilization period the controller captures a load cell signal and opens a timing window. At the end of the timing window the controller captures another load cell signal. A controller calculates the mass of the collected liquid over the collection period and the flow rate such as mass rate and / or the volumetric rate. The duration of the timing window depends on the measurement desired. Since the liquid wells up and overflows the weir, the system can make precise measurements of low flow rates. In another feature, feedback control mechanisms are implemented in the batch constant flow method or steady state constant flow method. In both methods, the instantaneous measured flow rate is compared with an input command derived from flow rate calibration, sending an error correction feedback signal to the controlled valves to actuate the flow rate of liquid supply and the drain and the gas pressure, until zero error or an acceptable error margin is reached or the desired flow rate is established.

An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.