59results about How to "Little latency" patented technology

Presented is a system and a method for load balancing multiple globally-dispersed servers based on client-centric performance criteria. The infrastructure of the system includes load balancing domain name servers (DNS-LBs) deployed in close physical proximity to the Internet service providers' points of presence. The DNS-LBs are then able to monitor the performance of the servers from a location close to the clients, which allows the DNS-LBs to select a server that will yield the best performance from that location for the client. A second level of the infrastructure utilizes domain name servers (DNS-Bs) that are deployed on the Internet backbones and regional provides. The authoritative domain name servers (DNS-As) for the servers to be load balanced refer all name queries to these DNS-Bs. The DNS-Bs then refer the queries to one of the DNS-LBs based on a mapping of the DNS-ISP address to its physically proximate DNS-LB. The DNS-LB then returns the IP address of the server that will provide the best performance from that location.

A system and method for peer-to-peer communications in cellular communications systems are provided. A method for communications device operations includes receiving a peer list at a communications device, where the peer list includes a list of reachable communications devices and device-to-device (D2D) capability information of the reachable communications devices, selecting a peer from the peer list, sending a content request comprising an indication of a content to a communications controller serving the communications device, and receiving the content from the peer over a channel established by the communications controller.

The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

In order to solve a problem of an accumulation on the transmission side, a delay on the reception side, and the like at the time of transmission in a communication system such as a wireless LAN system, each communication station in a network transmits a beacon in which information with respect to the network is written and sets a state in which a reception operation is performed during periods of time before and after the transmission of the beacon signal when performing access control not to make communication timing of a packet collide with that of another station by detecting a signal transmitted from another station. With performing such processing, a system can be formed based on minimum level of transmission and reception operation when transmission and reception data does not exist in each communication station in the network, and also a data transfer can be performed with latency as small as possible in a minimum necessary level of transmission and reception operation by making a transition of a transmission and reception state in accordance with a fluctuating volume of transmission and reception data.

In a stream data processing method in which part of stream data is defined as a processing target and the time control information which indicates the advance of the time is inserted into the stream data, time information of the received stream data is stored in a next ignition time holding area as an ignition time. A processing module for generating the time control information at a time different from the time of reception of the stream data is extracted out of a query that indicates how the stream data is to be processed. Based on the extracted processing module and the time information indicating the time of the reception of the stream data, the ignition time is calculated and stored in the next ignition time holding area. The time generation module inserts the time control information at the ignition time held in the next ignition time holding area.

The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same. The effect is that the arbitration between the different requests is rendered less complex. In embodiments of the memory controller there is also an average latency reduction for the high-priority requests. The invention further relates to a System-on-Chip comprising the memory controller, to a method of a refresh request generator for use in such System-on-Chip. The invention also relates to a method of controlling access of a System-on-Chip to a volatile memory, wherein the System-on-Chip comprises a plurality of agents which need access to the volatile memory, and to a computer program product comprising instructions for causing a processor to perform such method.

An integrated circuit 2 is provided with multiple clock domains separated by a clock boundary 8. Data values are passed across the clock boundary 8 using a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundary 8 and must be synchronised to the receiving clock frequency. The clocks being used on either side of the clock boundary 8 may be switched and have a variable relationship therebetween. Multiple synchronisation paths are provided within pointer synchronising circuitry 32 which are used depending upon the particular relationship between the clocks on either side of the clock boundary 8. A pre-switch pointer value is held in a transition register 44 until a post-switch pointer value is available from the new synchronising path 36 when a switch in clock mode is made which requires an increase in synchronisation delay.

The present invention provides a new and unique method and apparatus for detecting in a short-range communication device, such as a WLAN station (STA), the trend in WLAN signal strength based on one or more characteristics, e.g. received signal strength values and current time of their observation, by fitting a generalized linear model to the values. Based on the detected trend, three things can be inferred: 1) WLAN radio coverage available for STA is strengthening, 2) WLAN radio coverage available for STA is stationary, or 3) WLAN radio coverage available for STA is weakening.

A memory controller 4 for a NAND memory array 2 includes error detecting circuitry having input circuitry 6, fast zero-error detecting circuitry 10, fast-path error correcting circuitry 16, 24, slow-path error correcting circuitry 18, 22 and fast-bad-block detecting circuitry 28.

The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield.

A data retention probe for a packet-switched, mobile telecommunications network employs interfaces to connect to interfaces carrying traffic on a mobile network side of a gateway node and on a global internet side of the gateway node. A FPGA creates for each packet at least one fingerprint of one or more fields that are unchanged as part of the address translation performed by the gateway node and to create informative metadata for those packets. A processing unit: (1) receives from the FPGA the fingerprints and metadata and maintains flow records for each flow of packets seen on each side of the gateway node; and (2) compares the fingerprints and, where a match is found, determines those packets to be part of the same communication session and creates a record correlating internal IP address or a subscriber identifier to external IP address and port number.

The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.

A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.

This invention uses fiber characteristics combined with knowledge of the 8b10b code to discover and compensate for skew between parallel data streams, caused by chromatic dispersion, in a WDM system allowing the receiver to recover both the data and timing of the data streams as they were originally launched. This skew discovery and compensation does not require the insertion or deletion of any control symbols to/from the original 8b10b streams, and does not require the use of a training or sample sequence.

Data transport is provided in a communication network such as a Network-on-Chip arrangement via full-duplex mesochronous links between routers. Request signals and response signals are exchanged between these routers acting alternatively as an initiator and a target operating in respective clock domains at opposite ends of respective full-duplex mesochronous links. The request initiator flow control signals are monitored at the target end of the link while the response target flow control signals are monitored at the initiator end of the link. The monitoring action involves ascertaining if a request has been granted at the initiator end of the link and if a response has been granted at the target end of said link thus correspondingly managing the data flow over the link.