182results about How to "Improve programmability" patented technology

An integrated multimedia, entertainment, communications and control system. The system is based on a general purpose computer and is capable of interfacing with, controlling or managing a wide variety of audio, video, telecommunications, data communications or other devices. The system includes a programming environment for creating services or user experiences that may incorporate features or functionalities of several devices that are conventionally operated as separate, standalone devices.

A switch fabric system comprises a first chassis for receiving a plurality of line cards each having a plurality of ports and at least two switch fabric cards wherein each line card comprises a plurality of link ports for linking the line card with the switch fabric card. Each switch fabric card provides a switching bandwidth. The system comprises a management unit for managing the traffic on the switch fabric cards wherein the management unit removes the traffic from one switch fabric card if the one switch fabric card is to be removed while the other switch fabric card operates and transfers the traffic to the other switch fabric card.

The invention discloses a realization method for NUMA (Non-Uniform Memory Access) structure based on distributed hardware-assisted memory virtualization. The method comprises the following four steps: step one, preparation stage; step two, normal work stage; step three, NUMA processing local request stage; and step four, NUMA processing remote request stage. The invention adopts the latest hardware-assisted memory virtualization technology and the distributed shared storage algorithm, provides a NUMA-structure shared single physical address space, and realizes the transparent and unified management to the multi-host memory resource by a guest operation system, so as to reduce the complexity of the application programming and increase the usability of system resource. Furthermore, the invention has the advantages of favorable use and development prospects.

The invention discloses a GPS signal large-scale parallel quick capturing method, which comprises the following steps: configuring a large-scale parallel quick capturing module firmware comprising submodules of multiplier, data block cache, parallel part correlative processing, frequency domain transformation, postprocessing and digital controlled oscillator, code generator and the like in a system CPU; through the calling computation, converting low-medium frequency digital signals into baseband signals in a processing procedure to combine a data block; performing zeroing extension of the length and the data block on each equational data section in the data block; then based on FFT transformation computation, performing parallel part correlative PPC processing on each extended data section and local spreading codes, and performing FFT transformation on each line of a formed PPC matrix to obtain a result matrix; and performing coherent or incoherent integration on a plurality of result matrixes formed by processing a plurality of data blocks to increase the processing gain, improve the capturing sensitivity, roughly determine the code phase and the Doppler frequency of GPS signals, and achieve two-dimensional parallel quick capturing of the GPS signals. The method has high processing efficiency and high capturing speed, and can be applied to various GPS positioning navigation aids.

A method of linking at least two network switches is disclosed, wherein each network switch switches data traffic of a plurality of devices, through a plurality of couplings. The method comprises the steps of generating a data stream including an identifier to be sent from a first to a second network switch, generating a number identifying one of the couplings from the identifier, and using the identified coupling for transfer of the data stream.

The invention provides a realization method for distributed memory virtualization technology. The method mainly adopts the latest virtualization technology of combing hardware and software together, conducts virtualization and integration to the memory resource distributed in a multi-host combining with distributed shared storage algorithm, provides a shared single physical address space for an upper grade guest operation system, and realizes the management and the use of the guest operation system to the distributed memory. The invention carried out innovation on the basis of the current mature technology, is simple to implement, and has excellent use and development prospects.

One greatest advantage of the three-dimensional memory (3D-M) is its integratibility. In a electrically programmable three-dimensional integrated memory (EP-3DiM), an electrically programmable 3D-M (EP-3DM) is integrated with an embedded RWM and/or an embedded processor. Collectively, the EP-3DiM excels in speed, density/cost, programmability and data security.

Method of and a compiler for controlling a network based on a logical network model. The network has physical nodes and logical nodes. The physical nodes are interconnected by physical links in accordance with a physical network layout. The logical network model has logical nodes indicated with a logical node name which refers to at least one physical node in the network. The method uses a depth-mapping relation defining how the logical nodes are mapped to the physical nodes. The method includes creating logical links between the logical nodes in dependence on the physical paths between the physical nodes and on the depth-mapping relation. The method uses edge-relationships between logical link, logical path, physical link, physical path and depth-mapping relations. Logical paths in the logical network are transformed into a physical path comprising of physical links between the physical nodes through recursive calculation and forwarding instructions are created for the physical nodes, in dependence on the edge-relationships and point-of-attachment names between physical links and physical nodes. A user of a compiler may specify additional operations other than switching, multiplexing or de-multiplexing to be performed at a logical node on packet or signal. Said packet or signal may be identified with a logical identifier identifying at least one logical link or logical path, and said additional operation may be specified at a logical node, providing programmability of additional operations in said logical network model. Said additional operations will, if possible, be performed by physical or virtual resources represented by physical nodes.

The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield.

A system and technique for providing to flexible, programmable frequency estimators and spectrum analyzers that can operate over extremely large bandwidths and yet provide high spectral resolution are described. The acquisition time and hardware complexity of one technique scale as O(N), where N denotes the number of frequency bins acquired. Embodiments are disclosed in which architectures are implemented using exponentially-tapered transmission lines and filter cascades.

The invention discloses a terahertz compressive imaging system and method. The system comprises 1, a terahertz generation and detection unit which comprises a laser source, a terahertz emitter and a terahertz detector, 2, a terahertz wave coding measurement unit which comprises a light splitter lens, a semiconductor mask plate and a digital projection device, wherein the digital projection device produces encoded pattern light beams, the light beams act on the semiconductor mask plate to cause semiconductor carrier distribution and the semiconductor mask plate allows the specific terahertz wave to go through the mask plate and keeps congruity of the specific terahertz wave and the light beam pattern so that terahertz wave spatial modulation is realized and a semiconductor mask plate coding function is realized, and 3, a terahertz reconstruction imaging unit which is used for recovering the original image through a reconstruction algorithm so that terahertz imaging is realized. Through combination of digital light processing projection and semiconductor photo-induced carrier characteristics, terahertz wave light-controlled modulation is realized. The system has the advantages of complete digitization, fast rate, high programmable capability, low cost and integration easiness.

The invention relates to a high-speed rail fastener detection and counting method and a high-speed rail fastener detection and counting system based on machine vision. The high-speed rail fastener detection and counting system comprises image acquisition equipment, a DSP embedded processing system and two LED lighting devices, and designs a rapid fastener detection method based on area and width characteristics of a fastener. Compared with a fastener positioning methods adopting a photoelectric encoder, a photoelectric ranging sensor, a GPS positioning system and the like, the fastener positioning method based on machine vision has the advantages of high positioning precision, no accumulative error, simple structure, easy establishment, high cost performance and the like. A fastener counting result obtained by the high-speed rail fastener detection and counting system is uploaded to an upper computer, a rail geometric parameter fault position obtained by a rail geometric parameter measurement sensor is marked, the maintenance position is provided for railway maintenance personnel quickly and precisely, and the high-speed rail fastener detection and counting method and the high-speed rail fastener detection and counting system are of great significance to safety early warning of the railway.

A programmable resistance memory includes a volume of programmable resistance material formed between and coupled to two electrodes. The volume of programmable resistance material includes a region of enhanced programmability that is positioned to maximize the effect of a programming current. The region of enhanced programmability is positioned at a distance from regions of high thermal conductivity, such as areas in close proximity to electrodes.

A system includes a filter and a tuner formed on an integrated circuit. The filter receives an input signal comprising a first number of channels and communicates an intermediate output signal comprising a second number of channels less than the first number of channels. The tuner is coupled to the filter and receives the intermediate output signal and communicates an output signal comprising a third number of channels less than the second number of channels.

The invention relates to an arbitrary waveform generator based on a PCI bus, which comprises the PCI bus being a local bus not attached to some a concrete processor. Structurally, the PCI is a primary bus which is inserted between a CPU and an original system bus, management on the layer is concretely realized by a bridge circuit, and an interface between top and bottom is realized to coordinate data transportation. An application layer buffer zone can continuously exchange data. The process of the data transportation is sponsored by an application layer program, but is executed by a chip PLX9054 of a PCI bridge interface, application layer software can carry out data generation and allocation in the process, and the whole transportation process is completed by direct memory access (DMA) and interruption. By utilizing the buffer zone to fast exchange the data, the arbitrary waveform generator can fast carry out data exchange, efficiently ensures the continuity of space signals and the fast switch of multiple signals, and has the advantages in multiple aspects such as flexibility, rapidness, changeability, controllability, high accuracy, and the like.

A method and apparatus for selective programmable filtering using analog circuits with time-varying components (e.g., resistances, capacitances) is presented. An analog front end receives an electronic signal and filters said signal by a passive or active continuous-time filter, having a combination of equivalent memory-less (e.g., resistive) and memory (e.g., capacitive or inductive) elements. A variable resistor circuit allows switching through a range of values to control one or more of the equivalent resistances of the passive or active continuous-time filter. The variable resistors are controlled using a control circuit to periodically modulate the resistances in the continuous-time filter between periodic sampling instances, such as during analog to digital conversion. Such periodic modulation of the resistances in the continuous-time filter allows for the programming and enhancement of the selectivity of said filter.

The invention designs a knuckle movement module of a five-finger dextrous hand based on the structural features and kinetic characteristics of a worm wheel and worm mechanism. Movement functions of all fingers are satisfied, additionally, the space structure of knuckles can be optimized to the maximum, the used worm wheel and worm mechanism has a self-locking function, and therefore, the designed knuckle movement module of the five-finger dextrous hand can achieve the poweroff self-locking function, so that the grasping ability of the dextrous hand is increased, and the movement and grasping requirements of the five-finger dextrous hand are satisfied. A worm wheel and worm speed reducer which is used as a driving unit of the knuckle module is mainly composed of a worm wheel, a worm, a gear, a shaft, a bearing, a box body and accessories and can be divided into three basic structures including the box body, a worm wheel and worm gear set and the combination of the bearing and the shaft, wherein the box body is a base of all parts in the worm wheel and worm mechanism and is an important part for supporting and fixing shaft components, guaranteeing correct positions of all transmission parts and supporting loads which act on the speed reducer; the worm wheel and worm gear set is used for transferring output power of a motor and changing the direction of the output power; the combination of the bearing and the shaft is mainly used for transferring power, supporting operation and improving the efficiency.

A high-precision timing interval measurement PCI card belongs to the measurement technology field. Hardware (4) includes PCI bus bridging module (2) with the core PCI9054, high-precision timing interval measurement module (1) with the core TDC-GP1, and core interface logic module (3) with the core XC3S400 FPGA; the hardware (4) comprising the timing interval measurement module (1), PCI bus bridging module (2), and interface logic module (3) is inserted in the PCI slots (6) of the computer (5), and under the control of the Linux operating system drivers and application software (7), it achieves high-precision timing interval measurement. The advantages are that it has high transmission speed, meeting the high-speed timing interval measurement application; and strong programmability, with good portability; strong functional scalability, and according to different applications, designing corresponding application software to facilitate the application in other areas.

The electrically programmable three-dimensional memory (EP-3DM) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, EP-3DM has minimum impact to the layout of the CUT. Apparently, CUT with integrated EP-3DM supports IC self-test. Moreover, with a large bandwidth with the CUT, EP-3DM-based IC self-test enables at-speed test.

The invention discloses a high-speed collection board based on electronic filtering technology, and a collection processing method. The collection board comprises an ARM chip, a client, a server, a pre-amplifier, a follower, a differentiating circuit, a first stage amplifier, a second stage amplifier, a reverse amplifier, an analog-digital converter, an FPGA and a GPU, wherein the pre-amplifier, the follower, the differentiating circuit, the first stage amplifier, the second stage amplifier, the reverse amplifier, the analog-digital converter, the FPGA and the GPU are sequentially connected. The FPGA and the GPU are connected to the client through a serial port and the ARM chip, and the client transmits an instruction to the FPGA or the GPU, and controls the processing process of a pulse signal. The client and the server carry out the bidirectional communication through a network. The collection board makes the most of the GPU to support floating calculation, and is high in programmability. The collection board achieves the multi-thread calculation, and is high in calculation speed. The collection board is high in data transmission speed. In order to solve a problem of pulse accumulation, the method provides the reliable hardware basis. The collection board can overcome the technical difficulty of pulse accumulation, improves the utilization rate of the pulse signals, and finally improves the detection precision of a system.

The invention provides a reusable logical gate based on an SET/MOS mixed structure according to a coulomb blockade oscillation effect and multiple-grid input features of the mixed structure of a single-electron transistor and an MOS transistor of a novel nano-electronical appliance. Through bias of an input end and a control end, all two-input logical functions of OR, NOR, AND, NAND, XOR and XNOR can be achieved by a logical unit without changing device parameters of a circuit, and only three PMOS transistors, three NMOS transistors and three SETs are consumed. The reusable logical gate is simple in structure, low in power consumption, high in integration level and high in reconfigurable features, and is expected to be applied to super-large-scale integration circuits with low power consumption and high integration density in future.