47 results about "Digital controlled oscillator" patented technology

The invention discloses an anti-radiation hardening digital controlled oscillator, a clock data recovery circuit and equipment, and the digital controlled oscillator is characterized in that an anti-radiation hardening circuit unit is connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), and comprises a voltage copying unit and a multiplexer; the voltage copying unit is used for copying a control voltage signal output by the digital-to-analog converter DAC, generating a copying voltage signal, sending the copying voltage signal to the multiplexer, and switching the output of the multiplexer from the control voltage signal to the copying voltage signal when the digital-to-analog converter DAC is subjected to single-particle bombardment. The DCO type clock data recovery circuit aims at solving the problem that a traditional DCO type clock data recovery circuit is prone to being affected by single particles when running in a radiation environment, single particle function interruption is generated, and consequently a space task fails, and the radiation hardening capacity of the DCO type clock data recovery circuit running in the radiation environment is improved.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

The invention relates to the field of electronic circuit design, and discloses a numerical control crystal oscillator circuit with low noise and high stability. According to the circuit, a two-stage voltage regulator is adopted to suppress power supply noise, wide-range high-precision frequency regulation is realized through thick and thin capacitor array regulation, oscillation signal quality is ensured through automatic detection feedback and external programming double-loop control, and a special oscillation starting circuit is arranged to accelerate the starting process of a crystal oscillator. Meanwhile, targeted optimization is carried out on a core circuit and layout in the loop, and noise and distortion are further reduced. The digital controlled oscillator can effectively solve the problems that an existing digital controlled oscillator scheme is narrow in frequency modulation range, large in phase noise and the like, the characteristics of low noise, high stability, rapid starting and the like are achieved, an excellent frequency reference is provided for a wireless communication and high-precision timing system, and the digital controlled oscillator has remarkable practical value.

The invention discloses a high-order QAM (Quadrature Amplitude Modulation) signal demodulation carrier synchronization design method based on secondary loop filtering, which relates to the field of signal processing, gives consideration to steady-state phase difference and capture bandwidth of carrier synchronization, covers various application scenes and provides good demodulation performance. According to the technical scheme, the method comprises the steps that a first loop is designed and mainly comprises a carrier compensator, a digital frequency discriminator, a numerical control oscillator, a first-stage digital loop filter and a frequency locking detector; the two-stage digital loop mainly comprises a carrier compensator, a digital phase discriminator, a numerical control oscillator, a two-stage digital loop filter and a phase locking detector. After the two stages of loops are connected in series, the first-stage loop carries out synchronous compensation on large frequency offset of signals, and the second-stage loop carries out synchronous compensation on small residual frequency offset and phase offset of the signals. The design is monitored through a locking detector, and carrier synchronization of high-order QAM signal demodulation is achieved.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

The invention discloses a digital control oscillator circuit based on a three-level tuning mechanism and a working method, and relates to the field of electronic engineering and signal processing. The working method of the digital control oscillator circuit comprises the following three steps: 1) a coarse adjustment stage: adopting a switched capacitor bank to realize preliminary adjustment of frequency, realizing large-range adjustment of the frequency, and providing reference frequency for subsequent fine adjustment; 2) second-stage adjustment: introducing an MOS capacitor to carry out finer capacitance fine adjustment, which is more direct than coarse adjustment, can quickly respond to the system, and optimizes the response speed and precision of the frequency; and 3) a fine adjustment stage: two MOS capacitors with controllable size difference are adopted for fine adjustment, the core is that the two MOS capacitors are controlled at the same time to realize complementation, and capacitance change can be generated by utilizing fine parasitic capacitance difference between the two MOS capacitors. Through the above three-stage adjustment mechanism, the digitally controlled oscillator can maintain low phase noise, realize seamless transition from coarse adjustment to fine adjustment, and accurately control frequency output.

The application discloses a kind of digital frequency tracking and synchronous sampling control system for resonant gyro, including self-excitation oscillation and automatic gain control device, preamplifier circuit and digital signal processor, digital signal processor includes first A / D conversion unit, second A / D conversion unit, frequency error detection unit FD, phase error detection unit PD, digital control oscillator NCO, sampling frequency generator and quadrature demodulation unit, the vibration signal of drive channel is handled after device output to first A / D conversion unit, conversion obtains the vibration signal after conversion, FD obtains frequency difference by frequency error detection, PD obtains phase difference by phase error detection, NCO is adjusted the frequency and phase of sampling frequency generator according to frequency difference and phase difference in real time, until the resonant frequency and phase of drive channel are tracked;The vibration signal of detection channel is handled after circuit output to second A / D conversion unit, obtains the vibration signal after conversion, and quadrature demodulation unit carries out quadrature demodulation and obtains speed signal.

The invention provides a frequency control method and system for a digital control oscillator, and relates to the technical field of frequency control of the digital control oscillator, and the method comprises the steps: obtaining a current gate period length value of the digital control oscillator, carrying out the gate control counting of an output clock of the digital control oscillator based on the current gate period length value, and obtaining an in-gate counting sequence, calculating a noise estimator based on the in-gate counting sequence, determining a target gate period length value based on the noise estimator, determining an instantaneous frequency ratio based on the target gate period length value, calculating a smoothing factor based on the noise estimator and the target gate period length value, and smoothing the instantaneous frequency ratio based on the smoothing factor to obtain a smooth frequency ratio; the target frequency tuning word is determined based on the smooth frequency ratio, the output frequency of the digital control oscillator is adjusted based on the target frequency tuning word, and the method has the effects of improving the dynamic performance, the steady-state precision and the environment adaptive capacity of frequency control of the digital control oscillator.

The application discloses an anti-radiation reinforced digital controlled oscillator, a clock data recovery circuit and equipment. The anti-radiation reinforced digital controlled oscillator is connected with an anti-radiation reinforced circuit unit between a digital-analog converter (DAC) and a voltage controlled oscillator (VCO). The anti-radiation reinforced circuit unit comprises a voltage replication unit and a multiplexer. The voltage replication unit is used for replicating a control voltage signal output by the digital-analog converter (DAC) and generating a replication voltage signal to be sent to the multiplexer. When the digital-analog converter (DAC) is subjected to single particle bombardment, the output of the multiplexer is switched from the control voltage signal to the replication voltage signal. The application aims to solve the problem that the traditional DCO type clock data recovery circuit is easily affected by single particles when running in a radiation environment, resulting in single particle function interruption and causing space task failure. The anti-radiation reinforced ability of the DCO type clock data recovery circuit when running in a radiation environment is improved.

A digital phase-locked loop includes a first clock divider, a decimation filter, a proportional integral filter, a signal conditioner, and a digitally controlled oscillator. The first clock divider divides a first clock signal including a first clock rate to generate a second clock signal including a second clock rate less than the first clock rate. The decimation filter converts an input signal at the first clock rate to an output signal at the second clock rate. The proportional integral filter filters the output signal at the second clock rate to generate a filtered output signal. The signal conditioner conditions the filtered output signal at the second clock rate to generate a conditioned output signal. The digitally controlled oscillator generates a carrier clock signal in response to the conditioned output signal.

The application relates to an improved ABSPD clock recovery method under single baud rate sampling, clock synchronization of transceiving end signals is realized through a full-digital type clock recovery loop, a timing error detector is used to replace numerical multiplication operation with symbol judgment and shift operation when calculating timing error e; after the timing error e is calculated by the timing error detector, the timing error e is input into a loop filter to remove noise and control words W are obtained; then the control words W are used to control a digital controlled oscillator, fractional interval mu k is calculated from the output NCO of the digital controlled oscillator and the control words W k The integer mark m k of the symbol and the calculated fractional interval mu k The received signal is interpolated in an interpolation filter, so that timing correct data are calculated. The application realizes ABSPD clock recovery under single baud rate sampling without multiplication operation, and significantly reduces the complexity of the whole clock recovery loop.

The present invention discloses a quantum measurement and control system based on RFSOC, specifically relating to the field of RFSOC control. The system includes an RFSOC chip, which integrates: a digital-to-analog conversion module, including eight 6.5GS / s digital-to-analog converters; an analog-to-digital conversion module, including eight 4GS / s analog-to-digital converters; an RF input module, connected to the digital-to-analog conversion module, including an RF input channel and a first signal conditioning circuit; and an RF output module, connected to the analog-to-digital conversion module, including an RF output channel and a second signal conditioning circuit. The digital-to-analog converter and the analog-to-digital converter are respectively connected to configurable IQ digital up / down conversion, a digitally controlled oscillator, a gain matrix, and decimation / interpolation filters. This invention fully leverages the advantages of the highly integrated RFSOC FPGA. It can be easily integrated into logic via an AXI interface. Furthermore, the present invention adds signal conditioning circuits to the DAC output and ADC output to achieve fine power adjustment.

The invention discloses a feed baseband rapid dynamic frequency offset compensation method and device. The device comprises a baseband unit and a radio remote unit. The baseband unit is responsible for frequency offset estimation and compensation amount calculation, the remote radio unit is composed of a CPU, an FPGA and an RFIC, the FPGA is used for digital intermediate frequency processing and a forward transmission interface, and the CPU completes parameter updating of an uplink numerical control oscillator and a downlink numerical control oscillator according to compensation information and achieves frequency offset correction of intermediate frequency signals so as to complete frequency offset compensation; then, the CPU controls the FPGA to send a real-time response message, and feeds back a compensation execution completion state to the baseband unit to form closed-loop control; according to the method, the special control frame is constructed in the eCRPI interface, so that the real-time dynamic compensation of the satellite feed baseband frequency offset is realized, and the stability and the high reliability of a satellite-ground link in a high-speed moving environment are ensured.

The present invention discloses a digital baseband and a qubit manipulator for low-temperature qubit manipulation. The digital baseband combines DDS and AWG modes, utilizing the DDS mode to achieve efficient frequency, phase, and amplitude adjustment, and the AWG mode to provide arbitrary waveform generation capabilities, thereby meeting the requirements of qubits when performing complex operations. Furthermore, since both the X-channel DDS module and the Y-channel DDS module of the XY driver have a digitally controlled oscillator, they can simultaneously generate independent digital intermediate frequency pulses, achieving frequency division multiplexing. This allows for direct output of simple sin waves, as well as reading waveform pulse data from the XY channel memory to output corresponding modulated pulse waveform data according to different requirements. Therefore, the present invention not only enables efficient and flexible qubit manipulation, but also enables multiple signals to share the same communication channel, optimizing channel utilization and thereby improving the overall transmission efficiency of the digital baseband.

The invention discloses a signal loop adjusting method and device, electronic equipment and a storage medium, and relates to the technical field of chips, the method is applied to an estimation module of a rotary transformer digital converter, and the method comprises the following steps: obtaining a first initial angle according to a sine output signal and a cosine output signal of a rotary transformer; acquiring a first initial angular velocity according to the at least two first initial angles and the sampling frequency of the analog-to-digital converter; and sending the first initial angle to the digitally controlled oscillator, and sending the first initial angular velocity to a loop filter, so that a signal loop of the resolver-to-digital converter performs a phase synchronization operation based on the first initial angle and the first initial angular velocity. According to the technical scheme provided by the embodiment of the invention, the construction time of a closed loop of the resolver digital converter is reduced, the response speed of a feedback control system in the resolver digital converter is improved, and the decoding efficiency of the resolver digital converter is further improved.

The embodiment of the invention discloses a frequency locking loop and a control method thereof, and the frequency locking loop comprises a numerical control oscillator which is configured to generate a corresponding target frequency signal based on a target control signal, and control a loop control switch to execute a corresponding action based on the frequency signal; the high-frequency counter is configured to count the numerical control oscillator to obtain an actual count value; an ideal count value unit configured to generate an ideal count value within a preset time window; the frequency identification unit is configured to judge whether the difference value between the actual count value and the ideal count value meets a preset difference value threshold value or not; and the frequency regulation control unit is configured to generate a target control signal based on a preset difference threshold value if the judgment result is satisfied, so as to control the numerical control oscillator to generate a target frequency signal. According to the frequency locking method and device, the technical problems that in the prior art, power consumption is large and the locking speed is low when frequency locking is carried out are solved.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

A method includes generating an output clock in a digitally controlled oscillator, dividing the output clock to generate a divided clock, generating a feedback clock based on the divided clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock includes connecting a first current source to a capacitor according to a fixed delay with respect to the divided clock, connecting a second current source to the capacitor prior to the fixed delay according to a first programmable select parameter, connecting a third current source to the capacitor prior to the fixed delay according to a second programmable select parameter, and generating the feedback clock based on a voltage of the capacitor after connecting the first, second, and third current sources to the capacitor.

An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.

The invention discloses a digital phase-locked loop system and a PLL output frequency modulation range real-time adjusting method thereof. The digital phase-locked loop system digitally controls an oscillator. The digital control oscillator comprises a plurality of groups of macro cells, and each group of macro cells comprises at least one macro cell; and each group of macro units is used for being switched on or switched off according to a configurable control signal input by a user, so that the switched-on macro units determine a PLL output frequency modulation range, and the PLL output frequency modulation range is adjusted according to an adjusting instruction input by the user. The effective frequency modulation range of the digital phase-locked loop system can be changed on the premise that a hardware circuit is not changed, so that the digital phase-locked loop system can flexibly adapt to various application scenes with huge differences, and the maximum application flexibility is obtained while the advantages of a single hardware design are kept.

The embodiment of the present specification discloses a digitally controlled oscillator calibration system. The system comprises a signal detection component, a phase discriminator, a digitally controlled oscillator gain module, a digital filter and a digitally controlled oscillator, wherein the digitally controlled oscillator is connected with the signal detection component, the signal detection component is connected with the phase discriminator, the phase discriminator is connected with the digitally controlled oscillator gain module, the digitally controlled oscillator gain module is connected with the digital filter, and the digital filter is connected with the digitally controlled oscillator. The embodiment of the present specification can not directly adjust the initial control word, but additionally generate a tuning control word for adjustment, so that the adjustment process is not affected by the size of the initial control word, and the adjustment can be performed with smaller code values, thereby improving the calibration accuracy.

A digital clock data recovery device for recovering a clock and data in a data signal includes a phase difference compensation unit configured to selectively output an upper bit value and a lower bit value of a phase difference value between a first input signal and a second input signal according to a condition based on a range of the phase difference value, a digital loop filter configured to receive an output of the phase difference compensation unit; and a digital controlled oscillator configured to transfer a feedback signal to the phase difference compensation unit based on an output value of the digital loop filter.

The present invention provides a digitally controlled oscillator (100), a synthesizer module (200), a synthesizer (300), and a method for generating an electronic audio signal. The oscillator (100) includes a digital processing device (10) capable of generating a first pulse wave at a first output terminal (PulseUp) of the processing device (10), wherein the first pulse wave includes pulses with at least two different frequencies. The oscillator (100) further includes a summing circuit (30) and a linear wave shaper (20). The output terminal (PulseUp) of the processing device (10) is connected to the summing circuit (30), and the summing circuit generates a total signal based on at least the first pulse wave. The total signal is fed to the linear wave shaper (20), and the linear wave shaper can generate an output signal at the output terminal (OUT) of the oscillator (100) by modifying the total signal.

The utility model provides a frequency hopping transmitting device and a frequency hopping communication system formed by the same, and relates to the technical field of radio communication, the frequency hopping transmitting device comprises a frequency hopping local oscillator unit, an L frequency band transmitting channel and a C frequency band transmitting channel, the frequency hopping local oscillator unit comprises a radio frequency transmitter, a radio frequency balun transformer, a first low-pass filter and a second low-pass filter, the radio frequency transmitter is composed of a digital control oscillator, an L-band local oscillator signal and a C-band local oscillator signal are respectively output to a first low-pass filter and a second low-pass filter through two radio frequency balun transformers, and the first low-pass filter transmits the L-band local oscillator signal to an L-band transmitting channel. And the second low-pass filter transmits the C-band local oscillator signal to the C-band transmitting channel. The frequency hopping local oscillator unit provided by the utility model takes the digital control oscillator as a core, has the advantages of small volume and low power consumption, and can greatly reduce the size of a filter without influencing the performance of the filter.

The application discloses an ASK 100% modulation communication system and method applied to a passive NFC tag. The application generates a recovered clock signal by introducing a high-precision digital control oscillator circuit, uses a carrier clock signal for timing control in a signal receiving process of the NFC tag, and switches to the recovered clock signal for timing control in a signal sending process, so that the passive NFC tag has a stable clock source during clock loss of ASK 100% modulation, and the normal work of a digital circuit can be ensured. Meanwhile, the application also introduces a digital clock calibration circuit, has relatively small area and power consumption under the premise of ensuring calibration frequency, and is more suitable for the development trend and requirement of low power consumption and low cost of the passive NFC tag. The application realizes the communication of the passive NFC tag with a PCD by using ASK 100% for load modulation, greatly improves the anti-interference ability of a signal, can optimize the requirement for a minimum antenna coupling coefficient k, optimizes the geometric alignment requirement of an antenna, and improves the long-distance communication ability of the tag.

This invention discloses a carrier synchronization design method for high-order QAM signal demodulation based on a two-stage loop filter, relating to the field of signal processing. It considers both steady-state phase difference and acquisition bandwidth for carrier synchronization, covering various application scenarios and providing good demodulation performance. This invention is implemented through the following technical solution: Loop one mainly includes a carrier compensator, a digital frequency discriminator, a digitally controlled oscillator, a first-stage digital loop filter, and a frequency lock detector; Loop two mainly includes a carrier compensator, a digital phase discriminator, a digitally controlled oscillator, a second-stage digital loop filter, and a phase lock detector. After the two loops are connected in series, the first-stage loop synchronously compensates for larger frequency offsets of the signal, while the second-stage loop synchronously compensates for smaller residual frequency and phase offsets. The lock detector monitors the design, achieving carrier synchronization for high-order QAM signal demodulation.

The application provides a digital control oscillator for a reconfigurable computing array, comprising a configuration module connected with a Cordic operation array, an output control module and an output cache module, and used for setting configuration information of the Cordic operation array, configuration information of the output control module and configuration information of the output cache module; the Cordic operation array is connected with the output control module, and used for generating a down-converted signal according to the configuration information of the Cordic operation array, and sending the down-converted signal to the output control module; the output control module is connected with the output cache module, and used for outputting the down-converted signal to the output cache module according to the configuration information of the output control module; and the output cache module is used for outputting a quadrature signal based on the down-converted signal according to the configuration information of the output cache module. The application further provides a signal generation method and electronic equipment, which can improve the NCO performance and reduce the NCO energy consumption.

A method includes causing a digital controlled oscillator to oscillate in a phase locked loop having a first closed loop transfer function, and changing the phase locked loop having the first closed loop transfer function to a phase locked loop having a second closed loop transfer function. The method also includes starting a charge-sharing locking process to correct phase errors in the digital controlled oscillator while the digital controlled oscillator oscillates in the phase locked loop having the second closed loop transfer function.