26 results about "Digital controlled oscillator" patented technology

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

The application discloses a kind of digital frequency tracking and synchronous sampling control system for resonant gyro, including self-excitation oscillation and automatic gain control device, preamplifier circuit and digital signal processor, digital signal processor includes first A / D conversion unit, second A / D conversion unit, frequency error detection unit FD, phase error detection unit PD, digital control oscillator NCO, sampling frequency generator and quadrature demodulation unit, the vibration signal of drive channel is handled after device output to first A / D conversion unit, conversion obtains the vibration signal after conversion, FD obtains frequency difference by frequency error detection, PD obtains phase difference by phase error detection, NCO is adjusted the frequency and phase of sampling frequency generator according to frequency difference and phase difference in real time, until the resonant frequency and phase of drive channel are tracked;The vibration signal of detection channel is handled after circuit output to second A / D conversion unit, obtains the vibration signal after conversion, and quadrature demodulation unit carries out quadrature demodulation and obtains speed signal.

The invention provides a frequency control method and system for a digital control oscillator, and relates to the technical field of frequency control of the digital control oscillator, and the method comprises the steps: obtaining a current gate period length value of the digital control oscillator, carrying out the gate control counting of an output clock of the digital control oscillator based on the current gate period length value, and obtaining an in-gate counting sequence, calculating a noise estimator based on the in-gate counting sequence, determining a target gate period length value based on the noise estimator, determining an instantaneous frequency ratio based on the target gate period length value, calculating a smoothing factor based on the noise estimator and the target gate period length value, and smoothing the instantaneous frequency ratio based on the smoothing factor to obtain a smooth frequency ratio; the target frequency tuning word is determined based on the smooth frequency ratio, the output frequency of the digital control oscillator is adjusted based on the target frequency tuning word, and the method has the effects of improving the dynamic performance, the steady-state precision and the environment adaptive capacity of frequency control of the digital control oscillator.

The application discloses an anti-radiation reinforced digital controlled oscillator, a clock data recovery circuit and equipment. The anti-radiation reinforced digital controlled oscillator is connected with an anti-radiation reinforced circuit unit between a digital-analog converter (DAC) and a voltage controlled oscillator (VCO). The anti-radiation reinforced circuit unit comprises a voltage replication unit and a multiplexer. The voltage replication unit is used for replicating a control voltage signal output by the digital-analog converter (DAC) and generating a replication voltage signal to be sent to the multiplexer. When the digital-analog converter (DAC) is subjected to single particle bombardment, the output of the multiplexer is switched from the control voltage signal to the replication voltage signal. The application aims to solve the problem that the traditional DCO type clock data recovery circuit is easily affected by single particles when running in a radiation environment, resulting in single particle function interruption and causing space task failure. The anti-radiation reinforced ability of the DCO type clock data recovery circuit when running in a radiation environment is improved.

The application relates to an improved ABSPD clock recovery method under single baud rate sampling, clock synchronization of transceiving end signals is realized through a full-digital type clock recovery loop, a timing error detector is used to replace numerical multiplication operation with symbol judgment and shift operation when calculating timing error e; after the timing error e is calculated by the timing error detector, the timing error e is input into a loop filter to remove noise and control words W are obtained; then the control words W are used to control a digital controlled oscillator, fractional interval mu k is calculated from the output NCO of the digital controlled oscillator and the control words W k The integer mark m k of the symbol and the calculated fractional interval mu k The received signal is interpolated in an interpolation filter, so that timing correct data are calculated. The application realizes ABSPD clock recovery under single baud rate sampling without multiplication operation, and significantly reduces the complexity of the whole clock recovery loop.

The invention discloses a feed baseband rapid dynamic frequency offset compensation method and device. The device comprises a baseband unit and a radio remote unit. The baseband unit is responsible for frequency offset estimation and compensation amount calculation, the remote radio unit is composed of a CPU, an FPGA and an RFIC, the FPGA is used for digital intermediate frequency processing and a forward transmission interface, and the CPU completes parameter updating of an uplink numerical control oscillator and a downlink numerical control oscillator according to compensation information and achieves frequency offset correction of intermediate frequency signals so as to complete frequency offset compensation; then, the CPU controls the FPGA to send a real-time response message, and feeds back a compensation execution completion state to the baseband unit to form closed-loop control; according to the method, the special control frame is constructed in the eCRPI interface, so that the real-time dynamic compensation of the satellite feed baseband frequency offset is realized, and the stability and the high reliability of a satellite-ground link in a high-speed moving environment are ensured.

A method includes generating an output clock in a digitally controlled oscillator, dividing the output clock to generate a divided clock, generating a feedback clock based on the divided clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock includes connecting a first current source to a capacitor according to a fixed delay with respect to the divided clock, connecting a second current source to the capacitor prior to the fixed delay according to a first programmable select parameter, connecting a third current source to the capacitor prior to the fixed delay according to a second programmable select parameter, and generating the feedback clock based on a voltage of the capacitor after connecting the first, second, and third current sources to the capacitor.

The invention discloses a digital phase-locked loop system and a PLL output frequency modulation range real-time adjusting method thereof. The digital phase-locked loop system digitally controls an oscillator. The digital control oscillator comprises a plurality of groups of macro cells, and each group of macro cells comprises at least one macro cell; and each group of macro units is used for being switched on or switched off according to a configurable control signal input by a user, so that the switched-on macro units determine a PLL output frequency modulation range, and the PLL output frequency modulation range is adjusted according to an adjusting instruction input by the user. The effective frequency modulation range of the digital phase-locked loop system can be changed on the premise that a hardware circuit is not changed, so that the digital phase-locked loop system can flexibly adapt to various application scenes with huge differences, and the maximum application flexibility is obtained while the advantages of a single hardware design are kept.

The embodiment of the present specification discloses a digitally controlled oscillator calibration system. The system comprises a signal detection component, a phase discriminator, a digitally controlled oscillator gain module, a digital filter and a digitally controlled oscillator, wherein the digitally controlled oscillator is connected with the signal detection component, the signal detection component is connected with the phase discriminator, the phase discriminator is connected with the digitally controlled oscillator gain module, the digitally controlled oscillator gain module is connected with the digital filter, and the digital filter is connected with the digitally controlled oscillator. The embodiment of the present specification can not directly adjust the initial control word, but additionally generate a tuning control word for adjustment, so that the adjustment process is not affected by the size of the initial control word, and the adjustment can be performed with smaller code values, thereby improving the calibration accuracy.

The utility model provides a frequency hopping transmitting device and a frequency hopping communication system formed by the same, and relates to the technical field of radio communication, the frequency hopping transmitting device comprises a frequency hopping local oscillator unit, an L frequency band transmitting channel and a C frequency band transmitting channel, the frequency hopping local oscillator unit comprises a radio frequency transmitter, a radio frequency balun transformer, a first low-pass filter and a second low-pass filter, the radio frequency transmitter is composed of a digital control oscillator, an L-band local oscillator signal and a C-band local oscillator signal are respectively output to a first low-pass filter and a second low-pass filter through two radio frequency balun transformers, and the first low-pass filter transmits the L-band local oscillator signal to an L-band transmitting channel. And the second low-pass filter transmits the C-band local oscillator signal to the C-band transmitting channel. The frequency hopping local oscillator unit provided by the utility model takes the digital control oscillator as a core, has the advantages of small volume and low power consumption, and can greatly reduce the size of a filter without influencing the performance of the filter.

The application discloses an ASK 100% modulation communication system and method applied to a passive NFC tag. The application generates a recovered clock signal by introducing a high-precision digital control oscillator circuit, uses a carrier clock signal for timing control in a signal receiving process of the NFC tag, and switches to the recovered clock signal for timing control in a signal sending process, so that the passive NFC tag has a stable clock source during clock loss of ASK 100% modulation, and the normal work of a digital circuit can be ensured. Meanwhile, the application also introduces a digital clock calibration circuit, has relatively small area and power consumption under the premise of ensuring calibration frequency, and is more suitable for the development trend and requirement of low power consumption and low cost of the passive NFC tag. The application realizes the communication of the passive NFC tag with a PCD by using ASK 100% for load modulation, greatly improves the anti-interference ability of a signal, can optimize the requirement for a minimum antenna coupling coefficient k, optimizes the geometric alignment requirement of an antenna, and improves the long-distance communication ability of the tag.

The application provides a digital control oscillator for a reconfigurable computing array, comprising a configuration module connected with a Cordic operation array, an output control module and an output cache module, and used for setting configuration information of the Cordic operation array, configuration information of the output control module and configuration information of the output cache module; the Cordic operation array is connected with the output control module, and used for generating a down-converted signal according to the configuration information of the Cordic operation array, and sending the down-converted signal to the output control module; the output control module is connected with the output cache module, and used for outputting the down-converted signal to the output cache module according to the configuration information of the output control module; and the output cache module is used for outputting a quadrature signal based on the down-converted signal according to the configuration information of the output cache module. The application further provides a signal generation method and electronic equipment, which can improve the NCO performance and reduce the NCO energy consumption.

A method includes causing a digital controlled oscillator to oscillate in a phase locked loop having a first closed loop transfer function, and changing the phase locked loop having the first closed loop transfer function to a phase locked loop having a second closed loop transfer function. The method also includes starting a charge-sharing locking process to correct phase errors in the digital controlled oscillator while the digital controlled oscillator oscillates in the phase locked loop having the second closed loop transfer function.

This invention relates to a multi-band finely tunable, wide-tuning-range numerically controlled oscillator, phase-locked loop, and chip. The numerically controlled oscillator includes n differential operational amplifier delay units, 2n array tuning circuits, and one digital-to-analog converter; the n differential operational amplifier delay units are cascaded, and the output V at the end of the cascade is... out +、V out - and the input V at the cascade start end in +、V in The positive and negative terminals of the circuit are reversed to form a ring structure; any one differential operational amplifier delay unit is connected to two array tuning circuits; a digital-to-analog converter is used to provide control voltage to the array tuning circuits. This invention significantly reduces oscillator phase noise through the combination of a tail current source and capacitor filtering, while simultaneously enabling a wide tuning range by adjusting the operating state of the array tuning circuits. The digital-to-analog converter achieves 256-bit fine-level voltage control, allowing for significantly precise operation of the output frequency, thus meeting the higher resolution requirements of a fully digital phase-locked loop.

The invention provides a low-power-consumption numerically-controlled oscillator, relates to the technical field of integrated circuits, and comprises a resonant cavity module used for generating a high-frequency resonant signal based on a resonator; the input end of the complementary cross-coupled oscillation module is connected with the resonant cavity module, and the complementary cross-coupled oscillation module is used for receiving high-frequency resonant signals and generating continuous oscillation; a capacitor array of the segmented numerical control capacitor tuning module is connected in parallel to two ends of the resonant cavity module and is used for receiving external numerical control signals and changing equivalent capacitance of a resonant network, so that wide-range and high-precision digital tuning is carried out on oscillation frequency; the parasitic oscillation suppression module is integrated in an internal feedback path of the complementary cross-coupled oscillation module and is used for suppressing direct-current positive feedback and attenuating low-frequency loop gain so as to eliminate direct-current locking and low-frequency parasitic oscillation; the input end of the output buffer module is connected with the output node of the complementary cross-coupling oscillation module, and the output buffer module is used for shaping and driving the oscillation signal and then outputting the signal. In the mode, wide tuning, ultra-low power consumption, high stability and high-precision tuning are realized, meanwhile, the phase noise performance and the mass production feasibility are improved, and the strict requirements of the battery-free Internet of Things node are met.

The application discloses a kind of feeding baseband fast dynamic frequency offset compensation method and device, including baseband unit and radio frequency remote unit;Baseband unit is responsible for frequency offset estimation and compensation quantity calculation, radio frequency remote unit is composed of CPU, FPGA and RFIC, the FPGA is used for digital intermediate frequency processing and front interface, CPU completes the parameter update of uplink digital controlled oscillator and downlink digital controlled oscillator according to compensation information, the frequency offset correction of intermediate frequency signal is realized, to complete frequency offset compensation;Subsequently, the CPU controls FPGA to send real-time response message, and the state of compensation execution completion is fed back to baseband unit, to form closed loop control;The application realizes the real-time dynamic compensation of satellite feeding baseband frequency offset by constructing special control frame in eCRPI interface, ensures the stability and high reliability of satellite-ground link under high-speed mobile environment.

The invention discloses a digitally controlled oscillator based on harmonic impedance tuning. The digitally controlled oscillator comprises a first MOS (Metal Oxide Semiconductor) tube, a second MOS tube, a transformer with a center tap, a coarse tuning capacitor bank, a middle tuning capacitor bank and a harmonic impedance tuning network, a source electrode of the first MOS tube is connected with a source electrode of the second MOS tube, and a source electrode common point is grounded through a harmonic impedance tuning network; the grid electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, and the drain electrode of the first MOS tube is connected with the grid electrode of the second MOS tube; a center tap of the transformer is connected with a VDD power supply; two ends of a primary coil of the transformer are respectively connected with a drain electrode of the first MOS tube and a drain electrode of the second MOS tube; the first end of the middle tuning capacitor bank is connected with the first end of the secondary coil of the transformer, and the second end of the middle tuning capacitor bank is connected to the second end of the secondary coil of the transformer. The invention has the advantages of high resolution and monotonous frequency tuning, and can optimize the phase noise performance.

The invention relates to the technical field of control circuits, and discloses a low-jitter two-stage LC-ring hybrid architecture phase-locked loop suitable for multi-channel SerDes, which comprises a frequency locking loop which comprises a time-to-digital converter, a digital control oscillator and a frequency control module, the output end of the digital control oscillator is connected to the first control end of the digital control oscillator through the time-to-digital converter and the frequency control module in sequence, and the digital control oscillator is used for achieving rapid coarse tuning of the frequency. According to the invention, a two-stage control architecture with separated frequency locking and phase locking is adopted, an LC-ring mixed DCO structure is combined, the ring oscillator is utilized to quickly converge the frequency in a frequency capture stage, and the LC oscillator is switched to provide a low-phase noise clock in a phase locking stage, so that the frequency of the low-phase noise clock is reduced. The contradiction between the locking speed and the output jitter of the traditional phase-locked loop in the high-speed SerDes application is effectively solved, and the clock generation efficiency and quality are remarkably improved.

The invention relates to a digital fractional-N phase-locked loop (PLL) (1) comprising:-a forward path comprising a phase discriminator (4), a digital loop filter (3), a digitally controlled oscillator (2); a feedback path comprising feedback elements (5, 6) wherein the phase discriminator output of the phase discriminator (4) is connected to the loop filter input of the digital loop filter (3) for providing an unfiltered control signal (Suf) and the loop filter output of the digital loop filter (3) is connected to the oscillator input of the digitally controlled oscillator (2) for providing a filtered control signal (Sf), wherein the unfiltered control signal (Suf) and the filtered control signal (Sf) each contain a periodic error signal having mutually different amplitudes; -a digital-to-time converter (7) arranged in a forward or feedback path and connected with a converter output to a phase discriminator input of the phase discriminator (4); -a spurious compensation unit (10) arranged with two inputs and an output, where a first input is arranged to receive an unfiltered control signal (Suf) and a second input is configured to receive a filtered control signal (Sf), where the spurious compensation unit (10) is arranged to determine a compensation signal (Sscop) along fractional phase instances of operation of the digital fractional-N PLL (1), and where the spurious compensation unit (10) is arranged to determine a compensation signal (Sscop) along fractional phase instances of operation of the digital fractional-N PLL (1). The spurious compensation unit (10) is further arranged to output the compensation signal (Sscop) to a converter input of the digital-to-time converter (7), or wherein the spurious compensation unit (10) is further arranged to inject the compensation signal (Sscop) into the unfiltered control signal (Suf) for compensating the periodic error signal.

Wireless communication devices have an all-digital phase locked loop (ADPLL) including a digital controlled oscillator, a counter, a time to digital converter, a phase detector, and a digital loop filter. The digital controlled oscillator (DCO) generates a DCO output signal (CKV) to synchronize with a reference clock signal (FREF), and the counter generates an integer part from CKV. The time to digital converter detects a time difference between a reduced frequency signal and FREF, where this reduced frequency signal is generated from CKV. The phase detector estimates a fractional part based on the time difference and derives a phase error based on the integer part from the counter, the fractional part, and a goal frequency. The digital loop filter receives the phase error and provides tracking codes to the DCO to adjust the frequency of its output signal.

The present disclosure relates to low-latency sub-sampling phase-locked loop. The invention relates to an apparatus, such as a sub-sampling phase-locked loop (PLL), comprising a digitally controlled oscillator (DCO), a digital phase detector, and a digital filter. The DCO generates a first signal having a phase based on a second signal provided to the DCO. The digital phase detector generates a third signal representing a phase offset between a reference clock signal and the first signal. The digital filter generates the second signal by filtering out high-frequency fluctuations in the third signal.

In a calibrated digital phase-locked loop (DPLL) circuit, during a normal mode of operation, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to maintain an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure the phase difference as a time interval. In a calibration mode of operation of the calibrated DPLL circuit, calibration of the resolution of the time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO remains constant. Calibrating the TDC in each of the DPLLs in an integrated circuit (IC) to nominal resolution in this manner improves synchronization of the clock domain. In some examples, the TDC circuit is a vernier-type circuit, and the calibration sets the delay difference to a nominal resolution.

The embodiment of the invention provides a frequency shift method and device of a numerically controlled oscillator and electronic equipment, and the method comprises the steps: calculating a target rotation phase value based on the serial number of a target input signal and a target frequency shift amount, and accurately obtaining the frequency change of a digital signal, the phase value recorded in the specified table and the reference phase value matched with the target rotation phase value are determined, the target reference phase value is obtained, under the limited storage depth of the specified table, the ideal phase value is as close as possible, calculation errors can be reduced, phase compensation is introduced, the searched target complex value is compensated, and the calculation accuracy is improved. And the target complex value is dynamically adjusted, and the compensated target complex value is used for performing frequency shift processing on the numerical control oscillator, so that phase errors can be effectively reduced, and spurious signals are reduced. Therefore, the technical problem of frequency shift result errors caused by low frequency shift precision in the prior art can be solved.

The application discloses a low-complexity noise-tolerant laser phase recovery method, and belongs to the technical field of signal processing.The application uses a two-stage structure to jointly estimate, realizes joint estimation of the frequency offset and phase of a signal carrier through phase estimation in a feedback stage and phase estimation in a feedforward stage, solves the problem of phase jump of a traditional Diff-4th algorithm at a low signal-to-noise ratio, and improves the carrier phase recovery performance.Based on a digital phase-locked loop and Viterbi-Viterbi phase estimation, compared with the traditional Diff-4th method, the application reduces the calculation complexity and the calculation resources.A phase detector, a loop filter and a digital controlled oscillator constitute a feedback loop, the carrier phase estimation is quickly adjusted in combination with a feedforward mechanism and a feedback mechanism, the Doppler shift caused by the relative motion of satellites is continuously tracked in real time, the constellation rotation caused by residual Doppler frequency offset and phase noise in an intersatellite coherent optical communication system can be eliminated, and compared with the traditional Diff-4th method, the stability and reliability of communication are improved.