Digital phase locked loop system and method

Abstract

A phase locked loop control system includes a digital controlled oscillator (DCO) that is controlled by logic cells in response to comparison of the oscillator output with a reference clock related signal. Delay cell number adjustment, delay cell load adjustment and cycle control are operative to digitally control the DCO frequency to obtain wide frequency range and limited jitter.

Description

BACKGROUND[0001]This disclosure is related to controlling an output signal with frequency and phase precisely related to the frequency and phase of an input “reference” signal, more particularly to phase locked loop (PLL) control.[0002]PLL control circuits are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Traditionally, the PLL circuit has been an analog block, including the basic components of a voltage control oscillator (VCO), phase and frequency detector (PFD), charge pump, low pass filter (LPF) and a feedback path. However, such analog PLL circuits comprise a plurality of capacitors which require a significantly large chip area. Additionally these circuits are very sensitive to power noise.[0003]More recently, PLL circuit design has evolved to a greater use of digit...

AI Technical Summary

Benefits of technology

[0005]The needs described above are fulfilled, at least in part, by use of a phase locked loop control system comprising a digital controlled ring oscillator that is controlled in response to comparison of the oscillator output with a reference clock related signal, by use of a digital phase and frequency detector. The ring oscillator frequency may be adjusted through a combination of varying the number delay cells coupled to the loop and the amount of loading on the cells. Phase adjustment can be obtained by selectively controlling the oscillator load during each clock cycle, thereby providing great precision in tuning the oscillator output frequency. In one embodiment, the basic ring oscillator circuit is made up of NAND gates thereby making it possible for the oscillator output to be reset in a short time and hence mitigate the effects of any drifts in the output clock.

Problems solved by technology

However, such analog PLL circuits comprise a plurality of capacitors which require a significantly large chip area.

Additionally these circuits are very sensitive to power noise.

The frequency of an external clock having accuracy required by such PLL circuit is limited with respect to its capability for applying a sampling rate that can accommodate high frequency reference clock signals.

Images