Synchronous digital multiplexer for on-frame multi plexing for multipath communication

A multi-channel communication and synchronous digital technology, which is applied in multiplex communication, time-division multiplex system, synchronization device, etc., can solve the problems that the equipment cannot be monitored uniformly, the multiplexing efficiency is low, and the up and down channels are complicated. Achieve the effects of low technical difficulty of equipment, simplified multiplexing structure, and simple frame structure

Inactive Publication Date: 2004-01-28
严尔林
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

PDH has three major disadvantages: (1) There are multiple multiplexing systems in the world (such as 1.544Mb/s in North America, 2.048Mb/s in Europe, 1.544Mb/s in Japan, etc.), and devices with different multiplexing systems are not compatible; (2) The amount of equipment is large, and the up and down channels are complicated; (3) There are not enough overhead bytes, and the network management capability is poor, and the equipment of various manufacturers cannot be uniformly monitored
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Method used

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  • Synchronous digital multiplexer for on-frame multi plexing for multipath communication
  • Synchronous digital multiplexer for on-frame multi plexing for multipath communication
  • Synchronous digital multiplexer for on-frame multi plexing for multipath communication

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Embodiment Construction

[0018] An embodiment is illustrated in conjunction with the accompanying drawings:

[0019] According to the frame multiplexing method as shown in Figure 1-③, under the control of the synchronous clock, each tributary stream is queued, and the first line of the first frame of the multiplexer writes 256 bits of the first frame of the first tributary stream, and the second line writes Enter the 256 bits of the first frame of the 2nd tributary, ... the 64th line writes the 256 bits of the first frame of the 64th tributary. The second frame of the multiplexer writes the 256 bits of the second frame of each tributary respectively, thus multiplexing 64 tributaries.

[0020] The frame structure is shown in Figure 2. It adopts a rectangular structure similar to SDH. Each frame has 64 rows, 34 columns, 125us, and the rate is 139264Kb / s. Columns 1 and 2 are overhead columns, with a total of 128 bytes. Among them, the overhead codes in column 1 from row 1 to row 41 are: A 1 、A 1 、A ...

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Abstract

The frame structure is a rectangle structure: 64 rows/frame, 34 columns, 139264 kb/s. the first and second columns are the overhead. 3th-34th columns are affluent information. Under control of synchronous clock, each affluent is queuing. First row of first frame is written into 256 bits of first frame of first affluent, and second row of first frame is written into 256 bits of first frame of second affluent and so on. In multiple connection procedure, with decoded to NRZ code, under control of main clock, each affluent is written to own buffer register. Then, under control of synchronous multiple connection clock, the procedure is continued to enter each queue equipment, mixer and encoder to output codes. The method overcomes the shortcomings of PDH and is better than SDH, providing features of less investment, good compatibility and lower technical difficulties.

Description

(1) Technical field [0001] The invention belongs to the technical field of multiplexing communication, and relates to a synchronizing device in a time division multiplexing system, in particular to a synchronous digital multiplexer for frame-based multiplexing of multiplexed communications. (2) Background technology [0002] The asynchronous multiplexer (PDH) is widely used on the existing multiplexed communication transmission lines, and this multiplexer adopts the method of "multiplexing by bit" (that is, multiplexing by bit). For example, the patent application number is 93106839 "Synchronous Multiplexing Method and Device for Adjusting Frame Structure Using Positive (or Negative) Code Rate". The bitwise (bit) multiplexing method is shown in Figure 1①. When multiplexing, first write the first bit of the first tributary, then write the first bit of the second tributary, ... and finally write the first bit of the last tributary; then write The 2nd bit of the 1st tributary,...

Claims

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Application Information

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IPC IPC(8): H04J3/06H04L5/00H04L7/00
Inventor 严尔林
Owner 严尔林
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