Encryption-decryption coprocessor for SOC, implementing method and programming model thereof

A coprocessor, encryption and decryption technology, applied in the field of ultra-large-scale digital integrated circuits, can solve the problems of increased power consumption and chip area, and achieve the effect of low power consumption and small hardware scale

Inactive Publication Date: 2008-06-18
边立剑 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, the realization of most SOC chips in this field adopts a hardware IP (hardware intellectual property module) or a coprocessor to implement an encryption and decryption algorithm architecture, which leads to an increase in chip area and power consumption.

Method used

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  • Encryption-decryption coprocessor for SOC, implementing method and programming model thereof

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Embodiment Construction

[0033] As shown in the figure, the encryption and decryption coprocessor applicable to SOC design of the present invention includes a bus interface and a configuration register, a central control module, a 32-bit ALU (operator) and a barrel shifter, a 256-bit processor, a 256 Bit sorter, 32-bit multiply, multiply accumulate and field multiplier, internal bus, data buffer, register file, DMA (direct data transfer) controller.

[0034] The bus interface (that is, the coprocessor interface) and the configuration register are connected to a general-purpose CPU (central processing unit) bus. The general-purpose CPU bus includes a 32-bit data input bus, a 32-bit data output bus, and a 32-bit address bus. Control signals include CS (chip select), RW (read and write), INT (interrupt) and SEL (data granularity). The general-purpose CPU bus can be easily connected with various popular CPU bus architectures, such as AHB and APB of ARM, WISHBONE of OpenCore and OPB of IBM, etc.

[0035] ...

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PUM

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Abstract

The invention discloses a coprocessor used for decryption and encryption of an SOC, an accomplishing method and a programming model. A bus interface is connected with a general CPU bus and receives read-write order from the general CPU bus; a central control module is used for controlling the read-write order received by the bus interface and triggering the start, implementation and stop of the corresponding action of the coprocessor; a 256 bits bit processor implements the common data retrieval and hash algorithm in the encryption algorithm and the digital signature algorithm; a DMA controller is connected with a second general CPU bus and conducts data processing under the control of the central control module. The accomplishing method divides various encryption-decryption algorithms into various hardware arithmetic units which are controlled and dispatched by software. The programming model is the description of a register. The invention is more flexible and economic, can realize most known encryption-decryption algorithms and can meet the design requirements of most SOC chips.

Description

technical field [0001] The invention relates to a very large-scale digital integrated circuit (VLSI), in particular to an encryption and decryption coprocessor suitable for designing and integrating an SOC (system on a chip) in a very large-scale digital chip. The invention also relates to the realization method of the coprocessor and the programming model used for the method. Background technique [0002] At present, there is no similar patent in this field in China. Foreign patents in this field mostly focus on specific implementations of specific encryption and decryption algorithms (high-speed implementation, low-power implementation, etc.). These patents are characterized by strong specificity and high speed, but a hardware structure can only be used for one or two algorithms (such as DES, RSA, ECC, etc.), which are suitable for very strong real-time requirements. [0003] At present, most SOC chips in this field use a hardware IP (hardware intellectual property modul...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78
Inventor 边立剑张立军
Owner 边立剑
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