126 results about "Chip select" patented technology

The invention provides an inference system and method of a large language model based on multi-chip parallel computing, and relates to the technical field of artificial intelligence. The system comprises a pre-calculation module used for processing input instruction information to generate to-be-reasoned data, and the to-be-reasoned data is in a matrix form; the expert parallel module is used for sending the to-be-reasoned data to accelerator chips in the expert parallel module and determining sub-reasoning data processed by the activation expert units corresponding to the accelerator chips respectively, so that the activation expert units carry out calculation based on the corresponding sub-reasoning data and complete parallel calculation result data is determined. The input data is broadcasted to all the accelerator chips, each accelerator chip selects the corresponding input data for calculation according to the set activation expert unit, the same complete calculation result is obtained through global protocol operation among all the accelerator chips, and the overall operation performance and efficiency are improved.

The application provides a computer system and a multi-server shared storage system, which can be applied to the technical field of server storage. The computer system comprises: a computer system, a non-volatile memory and a plurality of servers which are electrically connected; an arbitration module is used for determining a target server according to a plurality of access signals of the plurality of servers, and sending an authorization signal to the target server and a bus buffer module; the bus buffer module is used for connecting a transmission bus between the target server and the non-volatile memory according to the authorization signal; in the case that a chip select signal in a flash signal is at an effective level, an access address is obtained from the flash signal, the access address is configured by using a configuration partition base address to obtain a target access address, signal conversion is performed on the target access address, a target flash signal is obtained and sent to the non-volatile memory, so that the non-volatile memory manages data stored in a storage partition corresponding to the target access address.

The invention discloses a packaging method for suppressing residual vibration of a vibrating diaphragm, which relates to the technical field of chip packaging and comprises the following steps of: painting glue: painting patch glue on a carrier according to a preset thickness; and embedding the chip: inversely buckling the chip to enable the lining body of the chip to be embedded into the patch, enabling the vibrating diaphragm of the chip to be parallel to the carrier, and ensuring that the sound hole in the carrier is located in the projection range of the vibrating diaphragm. The chip is embedded in the patch adhesive instead of being suspended on the patch adhesive, and the packaging process of the carrier is improved, so that residual vibration is effectively reduced; when the thickness of the patch glue and the glue climbing height range are determined, sound holes with different sizes can be selected according to chips with different frequencies; when the size of the sound hole is fixed, different patch adhesive thicknesses and adhesive climbing height ranges can be selected according to chips with different frequencies, and the practicability is high.

The application provides a serial multi-chip communication device applied to a signal chain chip and a corresponding method. It relates to the technical field of chip serial communication and solves the problems of line design complexity and increased hardware resource occupation in the prior art. The device comprises: a chip select differential negative end of a master controller and a chip select input end of a first-level chip are interconnected; a second-level chip forms a chip select series connection structure; a slave chip select output end of the first-level chip and a chip select input end of a first second-level chip of the chip select series connection structure are interconnected; a serial differential positive end, a clock signal output end and a feedback signal input end of the master controller are respectively interconnected with a slave input end, a clock signal input end and a slave output end of the first-level chip and each second-level chip. The application can reduce resource consumption, realize access to different slave chips and is easy to adjust and expand.

The present disclosure relates to the field of integrated circuits and discloses a command generation circuit and memory. The command generation circuit includes a command receiving module and a command decoding module. The command receiving module is configured to receive a first command address signal, a first chip select signal, and a clock signal, and sample and register the first command address signal and the first chip select signal based on the clock signal to obtain a second command address signal and a second chip select signal. The command decoding module is connected to the command receiving module and configured to receive and decode an on-chip termination command based on the second command address signal and the second chip select signal. The on-chip termination command is used to control on-chip termination in a non-target chip when the target chip is performing any one of at least two operations. The present disclosure can simplify circuits, reduce circuit power consumption and occupied area, and thus improve memory performance.

The invention provides a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method and a computer readable storage medium. The synchronous serial communication system includes: a host configured to provide a clock signal; and a plurality of cascaded slave machines, each slave machine comprises a first serial interface and a second serial interface, the first slave machine is coupled to the host machine through the first serial interface, for adjacent slave machines, the second serial interface of the upstream slave machine is coupled with the first serial interface of the downstream slave machine, and the second serial interface of the downstream slave machine is coupled with the first serial interface of the downstream slave machine. Each slave synchronously receives a clock signal from the host through the first serial interface and the second serial interface. According to the synchronous serial communication system, the SPI only communicates between the host and the first slave and between the two adjacent slaves, the number of the slaves is not limited by the number of chip selection signals provided by the SPI host, the communication speed is not limited by the farthest distance slave, the communication speed is not limited by the number of the slaves, the communication speed can be increased, and the communication efficiency is improved. The communication efficiency is improved.

This application relates to a chip control circuit, method, and memory chip. The chip control circuit includes a signal detection trigger module and a circuit enable control module. The signal detection trigger module detects address level transition signals based on address signals and outputs a chip wake-up signal in combination with a chip select signal. Then, the circuit enable control module controls the working state of the chip auxiliary circuit based on the chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit. This enables the chip auxiliary circuit to be woken up on demand, effectively reducing the ineffective power consumption of the chip in standby, low load, or no read / write operation scenarios. It solves the problem of high power consumption caused by the continuous operation of the chip detection circuit in the prior art, and can effectively improve the energy efficiency ratio of the chip and the battery life of the chip device.

In some aspects, a host device may transmit a clock signal having a first frequency to a memory device and, for a chip select training operation, transmit a chip select signal having a pattern including high pulses and low pulses. The host device may initiate, for a sampling window, a chip select training operation with the memory device using the clock signal and the chip select signal, the sampling window including a quantity of pulses of the chip select signal. The host device may obtain from the memory device, via a first data in or out (DQ) pin, an indication of a first result of the chip select training operation for the high pulses of the chip select signal, and obtain, via a second DQ pin, an indication of a second result of the chip select training operation for the low pulses of the signal. Numerous other aspects are described.

The utility model relates to the technical field of storage devices, in particular to an SATA (Serial Advanced Technology Attachment) and M.2 dual-interface storage device. A storage device with SATA (Serial Advanced Technology Attachment) and M.2 interfaces comprises a storage carrier plate, an SATA interface and an M.2 interface, the SATA interface and the M.2 interface are arranged on the storage carrier plate, a golden finger is arranged on the bottom side of the storage carrier plate, a fool-proof port is formed in the storage carrier plate, the storage carrier plate comprises a front surface and a back surface, the SATA interface is arranged on the front surface of the storage carrier plate, and the interface position of the SATA interface faces the fool-proof port. The SATA interface and the M.2 interface are arranged on the storage carrier plate, so that the storage chip can support two data transmission modes, the transmission rate of the SATA interface and the transmission rate of the M.2 interface are both higher than that of a traditional USB interface, more efficient data transmission can be achieved, the storage carrier plate is further provided with the power management chip and the super capacitor, and under the normal operation condition, the storage chip can be connected with the storage chip through the power management chip and the super capacitor. And the power management chip selects a conventional access power supply, starts a power-off protection mode after power failure, and calls the super capacitor to supply power.

The invention relates to a control signal to support a clock synchronization feature at self-refresh exit. A memory device is capable of implementing a technique to avoid errors caused by the exchange of at least two clock signals. For example, the memory device can be configured to delay the swap of the at least two clock signals, which can enable the memory device to swap the at least two clock signals (e.g., from an even clock signal to an odd clock signal, or from an even clock signal to an odd clock signal) during a duration in which no command is issued to the memory device. And vice versa). In some examples, a control signal can be used to trigger the exchange of the lock signal and the at least two clock signals. Thus, the memory device is capable of avoiding errors due to timing inconsistence associated with exiting the self-refresh mode, for example, during a chip selection operation.

This application discloses a driving method for a vehicle-mounted triple-screen e-ink display. The method includes: responding to an upload command initiated by a mobile terminal and receiving image data generated by the mobile terminal; generating complete image data based on the image data; automatically segmenting a single image in the complete image data into three sub-image data that match the three physically separate e-ink screens according to the display size of the vehicle-mounted triple-screen display; allocating the three sub-image data to the driving control channels of the corresponding e-ink screens and obtaining a display preparation state; after obtaining the display preparation state, triggering the corresponding e-ink screen to perform a refresh action through a chip select control signal according to the refresh mode selected by the mobile terminal, and obtaining the mode processing result. Implementing this embodiment of the application uses a single Bluetooth main control IC to drive three physically separate e-ink screens, resulting in low hardware cost, simple wiring, support for flexible multi-mode refresh, reduced unnecessary power consumption, and suitability for low-power display requirements in vehicle scenarios.

A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.

This invention provides a method, apparatus, electronic device, and storage medium for programming memory chips. The method includes: determining whether a first logical storage unit and a second logical storage unit receive a corresponding chip select signal; if neither the first nor the second logical storage unit receives the corresponding chip select signal, determining the physical bit width of the memory chip; if the physical bit width is a first preset bit width, simultaneously performing programming operations on the first and second channels corresponding to the memory chip; if the physical bit width is a second preset bit width, performing programming operations on the first and second channels corresponding to the memory chip respectively; if either the first or second logical storage unit receives the corresponding chip select signal, programming the memory chip according to the chip select signal. This method improves the flexibility and efficiency of memory chip programming and effectively ensures the signal integrity of each channel of the memory chip.

This invention relates to the field of data processing technology, specifically to a data reporting method, system, and storage medium for slave devices. The method includes: generating a clock signal before the slave select signals corresponding to multiple slave devices enter a low-level state; controlling the MISO ports of the multiple slave devices to a high-impedance state when the falling edge of the slave select signal detects that the clock signal is low; wherein each slave device has corresponding identification information; a master device sends candidate identification information to the slave devices through the MOSI port, allowing the multiple slave devices to compare the candidate identification information with their own identification information; if the candidate identification information matches the identification information of a candidate slave device, the candidate slave device adjusts its MISO port from the high-impedance state to a low level based on the candidate identification information, and reports a notification message indicating a data transmission request. This method allows a master device to access multiple slave devices without adding chip select and GPIO.

This invention discloses a data acquisition device and method with a single SPI port that can cascade multiple acquisition boards. It includes a master control board with an SPI interface and multiple acquisition modules with slave SPI interfaces. Each acquisition module also includes a chip select input (CS-IN) and a trigger output (TRI-OUT) pin. The master control only needs to directly select / trigger the first acquisition module. The sampling initiation of the remaining acquisition modules is completed by the preceding module via TRI-OUT→CS-IN relay. During the data return phase, each module, when enabled, sequentially transmits data with the master control via a shared SPI bus. Each acquisition board has a chip select input and a trigger output. Through hardware cascading, the sampling control is sequentially transferred between boards. By combining the chip select signal pulse width or pulse sequence with the board's state machine and timing logic, cascading control of multiple acquisition boards and multi-sampling rate configuration are achieved. This significantly improves system scalability under limited master control resources, simplifies the control process, and enhances system versatility and stability.

In the semiconductor device, when bridge select data contained in received data indicates on status of through output of bit data, i.e. output of bit data as it is intact, between a first bus and a second bus, first device-dedicated data contained in the received data is through-outputted to the second bus, and moreover, when the bridge select data indicates on status of the through output and when communication by a specified second serial communication method dedicated to the first device has been set to the semiconductor device, a clock signal synchronized with the through-outputted data as well as a chip select signal are outputted.

A chip packaging module comprises a packaging substrate, a first chip, a second chip and a conductive metal pad or a wafer pad. The packaging substrate comprises a first surface and a second surface which are opposite, and the first surface is provided with a plurality of golden fingers. The first chip is arranged on the first surface. The second chip is arranged on the side, away from the packaging substrate, of the first chip in a stacked mode. The conductive metal pad or the wafer pad is arranged on the surface, deviating from the packaging substrate, of the second chip. The conductive metal pad or the wafer pad is electrically connected with a chip selection signal of the second chip and is connected with the golden finger through a metal lead. The utility model also provides a semiconductor device comprising the chip packaging module. The pads of the first chip and the second chip are different in arrangement or size, but can be compatibly arranged on the same packaging substrate, so that the development process is shortened, and the development cost is saved.

The invention provides an SPI (Serial Peripheral Interface) communication method and system. The system comprises an SPI host and at least one SPI slave; the method comprises the following steps: an SPI host switches a first pin of a data signal line into an external interrupt input signal mode, and pulls down a chip selection signal of a target SPI slave in at least one SPI slave; when the target SPI slave detects that the chip selection signal is low level and the data is prepared, the second pin of the data signal line is switched to a common output mode, and an interrupt signal is sent to the SPI host through the data signal line; after the interrupt signal is sent, the second pin of the data signal line is switched to a data transmission signal mode; and when the SPI host detects interrupt signal input, switching the first pin of the data signal line into a data transmission signal mode, starting SPI communication with the target SPI slave, and receiving target data sent by the target SPI slave. Therefore, the data signal line is multiplexed into different signal modes, and the interrupt notification mechanism of the SPI slave is combined, so that the efficient communication between the SPI master and slave is realized on the basis of not adding a new signal line.

This invention provides a microelectromechanical device (MEMS) sensor testing device, comprising a testing device body, which includes: a sample placement area for placing N MEMS sensors; a communication switching unit including a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a third output terminal, and a controlled terminal; the first input terminal is electrically connected to the SDI terminal of the MEMS sensor; the second input terminal is electrically connected to the CS terminal of the MEMS sensor; the third input terminal is electrically connected to the SDO terminal of the MEMS sensor; and an SPI interface, whose SCK clock input terminal is electrically connected to the SCK terminal of the MEMS sensor, and whose slave signal input terminal, chip select terminal, and slave signal output terminal are electrically connected to the first output terminal, the second output terminal, and the third output terminal, respectively. Compared with the prior art, this invention can be compatible with testing of SPI three-wire and four-wire communication functions with only a four-wire SPI master control device.

The invention provides an optical scanning module circuit which comprises a control chip and a plurality of photosensitive chips which are configured to be connected in parallel, receive a chip selection signal and a data output enabling signal from the control chip and sequentially transmit a plurality of photosensitive signals to the control chip in a time-sharing manner, each of the plurality of photosensitive chips comprises a serial peripheral interface and a plurality of photosensitive pixel circuits, each of the plurality of photosensitive pixel circuits corresponds to one of the plurality of cylindrical lenses of one optical scanning module, and the cylindrical lens transmits light to the corresponding photosensitive pixel circuit; the control chip is connected in series with the plurality of photosensitive chips which are connected in parallel through a chip selection connecting line and a data output enabling connecting line so as to control the plurality of photosensitive chips which are connected in parallel in a time-sharing and multi-construction-site mode.

This invention relates to a method and system for implementing a DSMC communication interface between an RK3576 ARM and an FPGA. The system initiates DMA transfer and specifies the data read location on the ARM side, while the FPGA initializes the input port and bidirectional data bus. The ARM side sends the read address, and the FPGA performs clock conversion, chip select signal processing, and clock counting. It detects the read operation flag and switches the bus to output mode. The DRAM module reads data and returns it to the FPGA side, and the ARM side receives the data via DMA. The FPGA side dynamically identifies the transmitted data length and ensures clock synchronization to complete the data transmission. This invention solves the problems of high DSMC bus protocol overhead and low transmission bandwidth. By optimizing clock management and data transmission processes, it significantly improves bus bandwidth utilization, reduces transmission latency, and enhances system flexibility and data transmission efficiency, making it suitable for high-speed data transmission scenarios.

The application relates to the computer technical field and discloses a firmware loading method and device, a computer device and a storage medium, the method is applied to a security monitoring chip, the method comprises the following steps: performing firmware image verification on a plurality of baseboard flash memories of a baseboard management controller through a verification program, and obtaining a verification result of each baseboard flash memory; performing level adjustment on a chip select signal of each baseboard flash memory according to the verification result; receiving a starting signal of the baseboard management controller; determining a target baseboard flash memory for loading firmware from the plurality of baseboard flash memories according to the starting signal; if the verification result of the target baseboard flash memory indicates that the verification is successful, opening a first switch; and if the verification result of the target baseboard flash memory indicates that the verification fails, closing the first switch. The application solves the control conflict problem of the baseboard management controller and the security monitoring chip, and improves the stability of a server.

This invention discloses a method for noise reduction based on a high-precision voltage source matrix using an optical chip, comprising the following steps: S1, initializing the MCP23017 and configuring chip select and address select signals; S2, sending control signals via SPI to select the DAC8568 channel; S3, the DAC8568 converting the digital signal into an analog voltage signal; S4, amplifying the analog voltage signal; S5, adding noise-reducing capacitors for high-frequency noise filtering; S6, a regulated power supply module providing a stable voltage; S7, optimizing the PCB design, layering and shielding the wiring; S8, adjusting and calibrating the voltage output in real time. This invention, through a high-precision voltage source matrix control method based on the ESP32-S3 microcontroller and the DAC8568 chip, achieves precise adjustment, noise suppression, and voltage stability optimization of multi-channel voltage output, meeting the stringent requirements of high-precision equipment for voltage sources.

This invention discloses a DRAM testing method, comprising the following steps: acquiring timing parameters of a DRAM, wherein the DRAM has two RANKs, each RANK having a corresponding chip select pin and a clock enable pin; initializing the DRAM according to the timing parameters; testing the first RANK of the DRAM; after the test is completed, the DRAM controller enters a self-refresh mode; synchronizing the enable clock of the second RANK, activating the initial verification parameters of the second RANK, and switching the chip select clock from the first RANK to the second RANK to test the second RANK; after the second RANK test is completed, the DRAM controller exits the self-refresh mode. According to the DRAM testing method of this invention, switching tests between two RANKs can be performed, and the same address can represent the actual row and column addresses of two parts of the DRAM, thereby achieving a significant increase in the testable DRAM capacity.

The embodiment of the invention provides a method and a device for reducing delay under a command two-phase transmission mechanism. The method comprises the following steps: acquiring a clock signal of a target memory, a chip selection clock signal and delay time corresponding to command operation; in response to the received command signal sent by the target memory, analyzing the command signal according to the clock signal and the chip selection clock signal, and determining a command judgment signal; determining a shift signal according to the clock signal and the chip selection clock signal; determining a delay counting enable signal according to a relationship between the shift signal and a preset shift signal and delay time corresponding to the clock signal and the command operation; a command enable signal is determined according to the delay count enable signal and the command decision signal to perform a command operation at the command address according to the command enable signal. Therefore, the counting start time of the delay clock cycle counting is not influenced by the duration of analyzing the command signal, so that the time for executing the command operation can be accurately determined.

Systems and techniques for detecting connection failures for serially connected worker modules (WMs) are disclosed. A method for detecting connection failures for serially connected WMs includes driving a chip select (CS) signal at a known voltage level to a first IO port of a first WM of a chain of serially connected WMs, propagating the CS signal to a second IO port of the first WM, wherein the second IO port of the first WM is configured to be coupled to a first IO port of a second WM of the chain of serially connected WMs, and determining, based on detecting that a signal at a voltage level different than the known voltage level is present at the first IO port of the second WM, that a connection failure is present between the first WM and the second WM.

A signal drive circuit (400) includes a first transmit circuit (410) having an input (402) coupled to a source of a chip select signal and an output configured to switch within a first voltage range (406, 408) having a first amplitude; a second transmit circuit (420) having an input (412) coupled to a source of the chip select signal and an output configured to switch within a second voltage range (416, 408) having a second amplitude; and an output node (422) coupled to an output of the first transmit circuit (410) and an output of the second transmit circuit (420). The first amplitude may be lower than the second amplitude.

This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input / output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command / address decoder. The command / address decoders are configured to receive command and address signals from external contacts of the memory device. The command / address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command / address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command / address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

The embodiment of the invention relates to a serial data transmission method, device and system, electronic equipment and a storage medium, and the method comprises the steps: responding to a triggering data transmission operation, determining an address of a corresponding target storage area, and determining a data transmission direction; determining a target slave device where the target storage area is located from the at least two slave devices based on the address; selecting a target chip selection signal output port connected with the target slave device from at least two preset chip selection signal output ports; setting the level of the target chip selection signal output port as a first preset level; generating a data transmission instruction based on the address and the data transmission direction; and sending the data transmission instruction to the target slave device by using a serial data transmission port connected with the target slave device, and performing data communication with the target slave device. According to the embodiment of the invention, the conflict of data read-write addresses when the types of the slave devices are the same and the address spaces of the memories are the same can be avoided, and the accuracy of data read-write is improved.