273 results about "Chip select" patented technology

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

In some aspects, an electronic device may receive a clock signal having a first frequency. The electronic device may receive, for a chip select training operation, a chip select signal having a pattern including high pulses and low pulses. The electronic device may perform, for a sampling window, the chip select training operation using the clock signal and the chip select signal, wherein the sampling window includes a quantity of pulses of the chip select signal. The electronic device may provide, via a first data in or out (DQ) pin, an indication of a first result of the chip select training operation for the high pulses of the chip select signal. The electronic device may provide, via a second DQ pin, an indication of a second result of the chip select training operation for the low pulses of the chip select signal. Numerous other aspects are described.

The invention provides an inference system and method of a large language model based on multi-chip parallel computing, and relates to the technical field of artificial intelligence. The system comprises a pre-calculation module used for processing input instruction information to generate to-be-reasoned data, and the to-be-reasoned data is in a matrix form; the expert parallel module is used for sending the to-be-reasoned data to accelerator chips in the expert parallel module and determining sub-reasoning data processed by the activation expert units corresponding to the accelerator chips respectively, so that the activation expert units carry out calculation based on the corresponding sub-reasoning data and complete parallel calculation result data is determined. The input data is broadcasted to all the accelerator chips, each accelerator chip selects the corresponding input data for calculation according to the set activation expert unit, the same complete calculation result is obtained through global protocol operation among all the accelerator chips, and the overall operation performance and efficiency are improved.

An input / output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.

A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

The invention relates to the technical field of storage and provides an initialization method for an LPDDR5, electronic equipment and a medium. In order to deal with the problem of abnormal command identification, improvement on an initialization process of a low-power fifth-generation double-rate memory is provided, before command bus training is carried out, optimization design is carried out on an operation step of initializing a configuration mode register to write a command, and a delay training module is used for carrying out delay training on the command bus. Frequency division is performed on the clock signal on the clock signal link, the command address mode and the chip selection mode are widened, the clock signal after frequency division is delayed, the first numerical value is used as an adjustable parameter, and the accuracy and the stability of mode register write commands are improved. The method is beneficial for ensuring that the time sequence diagram of the write command of the mode register meets the time sequence requirement of the particles of the memory, and is beneficial for ensuring that the particles of the memory can be correctly configured and initialized before command bus training is started.

The invention relates to a flash program protection circuit and a flash program protection method, in particular to a flash program protection circuit and a flash program protection method in a power failure process of equipment, and solves the technical problem that an operation instruction of a flash chip is sent by mistake due to unstable core voltage of a main control chip in the power failure process of the equipment, so that the flash program is rewritten or erased. The single-pole double-throw analog switch is additionally arranged between the chip selection end of the main control chip and the chip selection end of the flash chip and / or between the data end of the main control chip and the data end of the flash chip, so that the main control chip is communicated with the chip selection end of the flash chip and / or the main control chip is communicated with the data end of the flash chip when the system is powered on, and is disconnected when the system is powered off; the chip selection signal and / or the data signal are / is disconnected, so that an operation instruction generated by the main control chip cannot be sent to the flash chip, and a flash program stored in the flash chip is prevented from being erased or rewritten.

In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.

The invention discloses a multi-device communication system and method, an electronic device and a storage medium, and the system comprises a first device which comprises a chip selection signal output end; the second device to the Nth device comprise chip selection signal input ends, signal output modules and redundant signal output ends which are connected in sequence, the chip selection signal input end of the second device is connected with any chip selection signal output end of the first device, and the chip selection signal input ends of the third device to the Nth device are correspondingly connected with the redundant signal output ends of the second device to the (N-1) th device; the signal output module outputs a low level or a high level; and after determining the accessed Mth equipment, the control module sets the chip selection signal input end of the Mth equipment to be low level and communicates with the Mth equipment. Therefore, the problems that if the number of access devices is increased, an expensive CPU or an IO expansion chip needs to be added, and the cost is increased in the scheme that the SPI controller is simulated through GPIO to access the devices are solved, more slave devices are supported by utilizing the attributes of the signal output ends of the slave devices, and the production cost is reduced.

In some aspects, a system may transmit, via a main device of the system, a first value of a chip select signal indicating chip select de-assertion. The system may transmit, via a target device of the system, an interrupt signal while the chip select line indicates the first value. The system may transmit, via the main device and via the chip select line, a second value of the chip select signal indicating chip select assertion. The system may perform, via at least one of the one or more data lines, one or more data operations based on the target device transmitting the interrupt signal. Numerous other aspects are described.

Systems and methods related to communication interface are provided. An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement including serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port; inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the I2C data port and the SPI data port are electrically coupled to a second connection port; pattern detection circuitry to detect a signal pattern at a third connection port, the third connection port electrically coupled to the SPI CS port; and selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.

The present invention provides an over-temperature protection circuit, an LED control circuit with the over-temperature protection circuit, and an LED lamp using the LED control circuit. The over-temperature protection circuit provided by the present invention includes a power supply; an LED load; an IC chip, the input pin is connected to the power supply, the output pin is connected to the LED load, and a first resistor is connected between the chip select pin and the GND pin; a switch circuit, including a field effect transistor; a voltage-stabilizing winding including a main coil and an auxiliary coil, the main coil is connected between the output pin of the IC chip and the load, and the same-name end of one end of the auxiliary coil and the main coil connected to the output pin of the IC chip is grounded; a thermistor circuit, one end of which is connected to the same-name end of one end of the auxiliary coil of the voltage-stabilizing winding and the main coil connected to the load, and the other end is connected to the chip select pin of the IC chip, and the resistance of the thermistor circuit decreases as the temperature rises. A freewheeling diode, the positive electrode of which is connected to the output pin of the IC chip, and the negative electrode of which is connected to the LED load.

The application provides a computer system and a multi-server shared storage system, which can be applied to the technical field of server storage. The computer system comprises: a computer system, a non-volatile memory and a plurality of servers which are electrically connected; an arbitration module is used for determining a target server according to a plurality of access signals of the plurality of servers, and sending an authorization signal to the target server and a bus buffer module; the bus buffer module is used for connecting a transmission bus between the target server and the non-volatile memory according to the authorization signal; in the case that a chip select signal in a flash signal is at an effective level, an access address is obtained from the flash signal, the access address is configured by using a configuration partition base address to obtain a target access address, signal conversion is performed on the target access address, a target flash signal is obtained and sent to the non-volatile memory, so that the non-volatile memory manages data stored in a storage partition corresponding to the target access address.

The invention discloses a packaging method for suppressing residual vibration of a vibrating diaphragm, which relates to the technical field of chip packaging and comprises the following steps of: painting glue: painting patch glue on a carrier according to a preset thickness; and embedding the chip: inversely buckling the chip to enable the lining body of the chip to be embedded into the patch, enabling the vibrating diaphragm of the chip to be parallel to the carrier, and ensuring that the sound hole in the carrier is located in the projection range of the vibrating diaphragm. The chip is embedded in the patch adhesive instead of being suspended on the patch adhesive, and the packaging process of the carrier is improved, so that residual vibration is effectively reduced; when the thickness of the patch glue and the glue climbing height range are determined, sound holes with different sizes can be selected according to chips with different frequencies; when the size of the sound hole is fixed, different patch adhesive thicknesses and adhesive climbing height ranges can be selected according to chips with different frequencies, and the practicability is high.

A control method and device compatible with charging of multiple batteries, comprising the steps of: an STM chip detecting in real time whether a charging pile charging head is electrically connected to a battery pack to be charged, the charging head electrically connecting to the battery pack to be charged, the STM chip selecting a charging type according to the type of battery to be charged, inputting the acquired real-time data of the battery pack into a trained convolutional neural network, the neural network adjusting the error parameter in real time according to the real-time data of the battery pack, thereby adjusting the voltage or current at the input end of the battery pack, and the STM chip controlling the electrical connection of the charging head according to the output result of the convolutional neural network. The present invention automatically and flexibly switches different charging modes according to different needs, and taking into account different battery parameters, significantly improves the charging efficiency and saves resources.

The application provides a serial multi-chip communication device applied to a signal chain chip and a corresponding method. It relates to the technical field of chip serial communication and solves the problems of line design complexity and increased hardware resource occupation in the prior art. The device comprises: a chip select differential negative end of a master controller and a chip select input end of a first-level chip are interconnected; a second-level chip forms a chip select series connection structure; a slave chip select output end of the first-level chip and a chip select input end of a first second-level chip of the chip select series connection structure are interconnected; a serial differential positive end, a clock signal output end and a feedback signal input end of the master controller are respectively interconnected with a slave input end, a clock signal input end and a slave output end of the first-level chip and each second-level chip. The application can reduce resource consumption, realize access to different slave chips and is easy to adjust and expand.

The utility model provides a chip fixture, relates to chip fixture technical field, the chip fixture includes mounting box, through groove, extrusion plate, spacing groove, reinforcing plate, support plate, the other extrusion plate is rotatingly connected with the support plate, the both sides of support plate are respectively provided with side plate, one side of two side plate is respectively provided with side rod, the side rod is provided with the spacing groove, the side rod is provided with the spacing groove, and the spacing groove is provided with the spacing groove. One ends of the two side rods are connected through an end plate, the two side portions and the top of the end plate make contact with the inner surface of the mounting box, a base is arranged in the mounting box, an adjusting rod is arranged on the mounting box, one end of the adjusting rod is rotationally connected with the base, the adjusting rod is in threaded connection with the end plate, and a vertical plate is arranged at one end of the side plate. When the device is used, the reinforcing plate with the proper thickness can be selected according to different chips so that the clamping and fixing effects on the chips can be better achieved, the angles of the two extrusion plates can be adjusted at the same time, angle adjustment is convenient and rapid, and the using effect is good.

The present disclosure relates to the field of integrated circuits and discloses a command generation circuit and memory. The command generation circuit includes a command receiving module and a command decoding module. The command receiving module is configured to receive a first command address signal, a first chip select signal, and a clock signal, and sample and register the first command address signal and the first chip select signal based on the clock signal to obtain a second command address signal and a second chip select signal. The command decoding module is connected to the command receiving module and configured to receive and decode an on-chip termination command based on the second command address signal and the second chip select signal. The on-chip termination command is used to control on-chip termination in a non-target chip when the target chip is performing any one of at least two operations. The present disclosure can simplify circuits, reduce circuit power consumption and occupied area, and thus improve memory performance.

A signal state switching method, circuit, apparatus, device, medium and product, the method comprising: performing a signal state switching operation on a chip selection signal of an external chip (300) through a signal processing circuit (200) connected between the microcontroller (100) and the external chip (300) when data transmission is performed between the microcontroller (100) and the external chip (300). In the method, a CPU in the microcontroller (100) is replaced by a signal processing circuit (200) to perform a state switching operation of a chip selection signal on an external chip (300), equivalently, an auxiliary circuit is added to the microcontroller (100) to automatically perform the state switching operation of the chip selection signal, so that resources of the CPU in the microcontroller (100) are released, the CPU can be fully used for data transmission processing, and data transmission efficiency is improved. According to the invention, multi-frame data can be sent by one-time multi-filling in an asynchronous communication manner, so that the use efficiency of a CPU in the microcontroller (100) is improved, and the utilization rate of CPU resources is also improved at the same time.

The invention provides a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method and a computer readable storage medium. The synchronous serial communication system includes: a host configured to provide a clock signal; and a plurality of cascaded slave machines, each slave machine comprises a first serial interface and a second serial interface, the first slave machine is coupled to the host machine through the first serial interface, for adjacent slave machines, the second serial interface of the upstream slave machine is coupled with the first serial interface of the downstream slave machine, and the second serial interface of the downstream slave machine is coupled with the first serial interface of the downstream slave machine. Each slave synchronously receives a clock signal from the host through the first serial interface and the second serial interface. According to the synchronous serial communication system, the SPI only communicates between the host and the first slave and between the two adjacent slaves, the number of the slaves is not limited by the number of chip selection signals provided by the SPI host, the communication speed is not limited by the farthest distance slave, the communication speed is not limited by the number of the slaves, the communication speed can be increased, and the communication efficiency is improved. The communication efficiency is improved.

This application relates to a chip control circuit, method, and memory chip. The chip control circuit includes a signal detection trigger module and a circuit enable control module. The signal detection trigger module detects address level transition signals based on address signals and outputs a chip wake-up signal in combination with a chip select signal. Then, the circuit enable control module controls the working state of the chip auxiliary circuit based on the chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit. This enables the chip auxiliary circuit to be woken up on demand, effectively reducing the ineffective power consumption of the chip in standby, low load, or no read / write operation scenarios. It solves the problem of high power consumption caused by the continuous operation of the chip detection circuit in the prior art, and can effectively improve the energy efficiency ratio of the chip and the battery life of the chip device.

In some aspects, a host device may transmit a clock signal having a first frequency to a memory device and, for a chip select training operation, transmit a chip select signal having a pattern including high pulses and low pulses. The host device may initiate, for a sampling window, a chip select training operation with the memory device using the clock signal and the chip select signal, the sampling window including a quantity of pulses of the chip select signal. The host device may obtain from the memory device, via a first data in or out (DQ) pin, an indication of a first result of the chip select training operation for the high pulses of the chip select signal, and obtain, via a second DQ pin, an indication of a second result of the chip select training operation for the low pulses of the signal. Numerous other aspects are described.

The utility model relates to the technical field of storage devices, in particular to an SATA (Serial Advanced Technology Attachment) and M.2 dual-interface storage device. A storage device with SATA (Serial Advanced Technology Attachment) and M.2 interfaces comprises a storage carrier plate, an SATA interface and an M.2 interface, the SATA interface and the M.2 interface are arranged on the storage carrier plate, a golden finger is arranged on the bottom side of the storage carrier plate, a fool-proof port is formed in the storage carrier plate, the storage carrier plate comprises a front surface and a back surface, the SATA interface is arranged on the front surface of the storage carrier plate, and the interface position of the SATA interface faces the fool-proof port. The SATA interface and the M.2 interface are arranged on the storage carrier plate, so that the storage chip can support two data transmission modes, the transmission rate of the SATA interface and the transmission rate of the M.2 interface are both higher than that of a traditional USB interface, more efficient data transmission can be achieved, the storage carrier plate is further provided with the power management chip and the super capacitor, and under the normal operation condition, the storage chip can be connected with the storage chip through the power management chip and the super capacitor. And the power management chip selects a conventional access power supply, starts a power-off protection mode after power failure, and calls the super capacitor to supply power.

The present disclosure provides a pixel island, a display device, and a light field display device. The pixel island includes: a driving layer including a power pad, a data pad, a clock pad, and a chip select pad; a logic processing circuit; and a plurality of pixel circuits. The power pad is used to supply power to the logic processing circuit and the pixel circuits; the data pad is used to provide data voltages to the pixel circuits; and the logic processing circuit is used to provide gate control signals to the pixel circuits based on clock signals from the clock pad and chip select signals from the chip select pad. A plurality of sub-pixels are electrically connected to the pixel circuits in a one-to-one correspondence.

The invention relates to a control signal to support a clock synchronization feature at self-refresh exit. A memory device is capable of implementing a technique to avoid errors caused by the exchange of at least two clock signals. For example, the memory device can be configured to delay the swap of the at least two clock signals, which can enable the memory device to swap the at least two clock signals (e.g., from an even clock signal to an odd clock signal, or from an even clock signal to an odd clock signal) during a duration in which no command is issued to the memory device. And vice versa). In some examples, a control signal can be used to trigger the exchange of the lock signal and the at least two clock signals. Thus, the memory device is capable of avoiding errors due to timing inconsistence associated with exiting the self-refresh mode, for example, during a chip selection operation.

Provided is a memory device including a chip select (CS) buffer that is configured to output a first internal chip selection signal, a command clock (CK) buffer that is configured to output an internal clock signal, a command / address (CA) buffer that that is configured to output a first internal command / address signal, a CA buffer controller configured to control on / off of the CA buffer based on the first internal chip selection signal, synchronize the first internal chip selection signal and the first internal command / address signal to the internal clock signal, and delay the phase of a second internal chip selection signal synchronized to the internal clock signal, and a command decoder configured to decode any one of the second internal chip selection signal, a phase-delayed third internal chip selection signal, and / or a second internal command / address signal synchronized with the internal clock signal.

A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock receiving circuit, configured to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal; a sampling and logic circuit, configured to perform two-stage sampling processing and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a chip select clock signal, where the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle; and a decoding circuit, configured to perform decoding processing and sampling processing on the to-be-processed command signal according to the to-be-processed chip select signal and the chip select clock signal to obtain a target command signal.

The utility model provides an energy meter, including a single-chip microcomputer and a power supply, and also including a plurality of analog switch chips connected to the single-chip microcomputer, each of the analog switch chips, each of the analog switch chips is provided with eight sampling circuits, the single-chip microcomputer is provided with a chip selection polling circuit, the chip selection polling circuit is provided with a plurality of connection nodes, and each of the analog switch chips is connected to one of the connection nodes. In the above energy meter, each analog switch chip can measure the energy of eight points simultaneously through eight sampling circuits, and through the chip selection polling circuit of the single-chip microcomputer, the data of the eight sampling circuits on each analog switch chip can be accessed separately and sequentially, thereby reducing the functional parameter requirements of the single-chip microcomputer and improving the performance.

This application discloses a driving method for a vehicle-mounted triple-screen e-ink display. The method includes: responding to an upload command initiated by a mobile terminal and receiving image data generated by the mobile terminal; generating complete image data based on the image data; automatically segmenting a single image in the complete image data into three sub-image data that match the three physically separate e-ink screens according to the display size of the vehicle-mounted triple-screen display; allocating the three sub-image data to the driving control channels of the corresponding e-ink screens and obtaining a display preparation state; after obtaining the display preparation state, triggering the corresponding e-ink screen to perform a refresh action through a chip select control signal according to the refresh mode selected by the mobile terminal, and obtaining the mode processing result. Implementing this embodiment of the application uses a single Bluetooth main control IC to drive three physically separate e-ink screens, resulting in low hardware cost, simple wiring, support for flexible multi-mode refresh, reduced unnecessary power consumption, and suitability for low-power display requirements in vehicle scenarios.

The invention relates to supporting multiple peripheral components in a synchronous serial communication system with a single chip select line. A synchronous serial communication controller, a synchronous serial communication peripheral component, and a computer-implemented method of enabling synchronous serial communication between the synchronous serial communication controller and the synchronous serial communication peripheral component are provided. An example synchronous serial communication controller includes a serial communication interface configured with a clock logic line, a data output logic line, a data input logic line, and a shared select line logic line. The shared select line logic line is electrically connected to the plurality of peripheral components. Chip identification data transmitted over the data output logic line indicates a selected one of the plurality of peripheral components.