79 results about "Chip select" patented technology

The invention provides an inference system and method of a large language model based on multi-chip parallel computing, and relates to the technical field of artificial intelligence. The system comprises a pre-calculation module used for processing input instruction information to generate to-be-reasoned data, and the to-be-reasoned data is in a matrix form; the expert parallel module is used for sending the to-be-reasoned data to accelerator chips in the expert parallel module and determining sub-reasoning data processed by the activation expert units corresponding to the accelerator chips respectively, so that the activation expert units carry out calculation based on the corresponding sub-reasoning data and complete parallel calculation result data is determined. The input data is broadcasted to all the accelerator chips, each accelerator chip selects the corresponding input data for calculation according to the set activation expert unit, the same complete calculation result is obtained through global protocol operation among all the accelerator chips, and the overall operation performance and efficiency are improved.

The application provides a computer system and a multi-server shared storage system, which can be applied to the technical field of server storage. The computer system comprises: a computer system, a non-volatile memory and a plurality of servers which are electrically connected; an arbitration module is used for determining a target server according to a plurality of access signals of the plurality of servers, and sending an authorization signal to the target server and a bus buffer module; the bus buffer module is used for connecting a transmission bus between the target server and the non-volatile memory according to the authorization signal; in the case that a chip select signal in a flash signal is at an effective level, an access address is obtained from the flash signal, the access address is configured by using a configuration partition base address to obtain a target access address, signal conversion is performed on the target access address, a target flash signal is obtained and sent to the non-volatile memory, so that the non-volatile memory manages data stored in a storage partition corresponding to the target access address.

The application provides a serial multi-chip communication device applied to a signal chain chip and a corresponding method. It relates to the technical field of chip serial communication and solves the problems of line design complexity and increased hardware resource occupation in the prior art. The device comprises: a chip select differential negative end of a master controller and a chip select input end of a first-level chip are interconnected; a second-level chip forms a chip select series connection structure; a slave chip select output end of the first-level chip and a chip select input end of a first second-level chip of the chip select series connection structure are interconnected; a serial differential positive end, a clock signal output end and a feedback signal input end of the master controller are respectively interconnected with a slave input end, a clock signal input end and a slave output end of the first-level chip and each second-level chip. The application can reduce resource consumption, realize access to different slave chips and is easy to adjust and expand.

The invention provides a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method and a computer readable storage medium. The synchronous serial communication system includes: a host configured to provide a clock signal; and a plurality of cascaded slave machines, each slave machine comprises a first serial interface and a second serial interface, the first slave machine is coupled to the host machine through the first serial interface, for adjacent slave machines, the second serial interface of the upstream slave machine is coupled with the first serial interface of the downstream slave machine, and the second serial interface of the downstream slave machine is coupled with the first serial interface of the downstream slave machine. Each slave synchronously receives a clock signal from the host through the first serial interface and the second serial interface. According to the synchronous serial communication system, the SPI only communicates between the host and the first slave and between the two adjacent slaves, the number of the slaves is not limited by the number of chip selection signals provided by the SPI host, the communication speed is not limited by the farthest distance slave, the communication speed is not limited by the number of the slaves, the communication speed can be increased, and the communication efficiency is improved. The communication efficiency is improved.

This application relates to a chip control circuit, method, and memory chip. The chip control circuit includes a signal detection trigger module and a circuit enable control module. The signal detection trigger module detects address level transition signals based on address signals and outputs a chip wake-up signal in combination with a chip select signal. Then, the circuit enable control module controls the working state of the chip auxiliary circuit based on the chip wake-up signal and the chip select signal, combined with the enable signal of the chip auxiliary circuit. This enables the chip auxiliary circuit to be woken up on demand, effectively reducing the ineffective power consumption of the chip in standby, low load, or no read / write operation scenarios. It solves the problem of high power consumption caused by the continuous operation of the chip detection circuit in the prior art, and can effectively improve the energy efficiency ratio of the chip and the battery life of the chip device.

In some aspects, a host device may transmit a clock signal having a first frequency to a memory device and, for a chip select training operation, transmit a chip select signal having a pattern including high pulses and low pulses. The host device may initiate, for a sampling window, a chip select training operation with the memory device using the clock signal and the chip select signal, the sampling window including a quantity of pulses of the chip select signal. The host device may obtain from the memory device, via a first data in or out (DQ) pin, an indication of a first result of the chip select training operation for the high pulses of the chip select signal, and obtain, via a second DQ pin, an indication of a second result of the chip select training operation for the low pulses of the signal. Numerous other aspects are described.

The invention relates to a control signal to support a clock synchronization feature at self-refresh exit. A memory device is capable of implementing a technique to avoid errors caused by the exchange of at least two clock signals. For example, the memory device can be configured to delay the swap of the at least two clock signals, which can enable the memory device to swap the at least two clock signals (e.g., from an even clock signal to an odd clock signal, or from an even clock signal to an odd clock signal) during a duration in which no command is issued to the memory device. And vice versa). In some examples, a control signal can be used to trigger the exchange of the lock signal and the at least two clock signals. Thus, the memory device is capable of avoiding errors due to timing inconsistence associated with exiting the self-refresh mode, for example, during a chip selection operation.

This application discloses a driving method for a vehicle-mounted triple-screen e-ink display. The method includes: responding to an upload command initiated by a mobile terminal and receiving image data generated by the mobile terminal; generating complete image data based on the image data; automatically segmenting a single image in the complete image data into three sub-image data that match the three physically separate e-ink screens according to the display size of the vehicle-mounted triple-screen display; allocating the three sub-image data to the driving control channels of the corresponding e-ink screens and obtaining a display preparation state; after obtaining the display preparation state, triggering the corresponding e-ink screen to perform a refresh action through a chip select control signal according to the refresh mode selected by the mobile terminal, and obtaining the mode processing result. Implementing this embodiment of the application uses a single Bluetooth main control IC to drive three physically separate e-ink screens, resulting in low hardware cost, simple wiring, support for flexible multi-mode refresh, reduced unnecessary power consumption, and suitability for low-power display requirements in vehicle scenarios.

This invention provides a method, apparatus, electronic device, and storage medium for programming memory chips. The method includes: determining whether a first logical storage unit and a second logical storage unit receive a corresponding chip select signal; if neither the first nor the second logical storage unit receives the corresponding chip select signal, determining the physical bit width of the memory chip; if the physical bit width is a first preset bit width, simultaneously performing programming operations on the first and second channels corresponding to the memory chip; if the physical bit width is a second preset bit width, performing programming operations on the first and second channels corresponding to the memory chip respectively; if either the first or second logical storage unit receives the corresponding chip select signal, programming the memory chip according to the chip select signal. This method improves the flexibility and efficiency of memory chip programming and effectively ensures the signal integrity of each channel of the memory chip.

This invention discloses a data acquisition device and method with a single SPI port that can cascade multiple acquisition boards. It includes a master control board with an SPI interface and multiple acquisition modules with slave SPI interfaces. Each acquisition module also includes a chip select input (CS-IN) and a trigger output (TRI-OUT) pin. The master control only needs to directly select / trigger the first acquisition module. The sampling initiation of the remaining acquisition modules is completed by the preceding module via TRI-OUT→CS-IN relay. During the data return phase, each module, when enabled, sequentially transmits data with the master control via a shared SPI bus. Each acquisition board has a chip select input and a trigger output. Through hardware cascading, the sampling control is sequentially transferred between boards. By combining the chip select signal pulse width or pulse sequence with the board's state machine and timing logic, cascading control of multiple acquisition boards and multi-sampling rate configuration are achieved. This significantly improves system scalability under limited master control resources, simplifies the control process, and enhances system versatility and stability.

A chip packaging module comprises a packaging substrate, a first chip, a second chip and a conductive metal pad or a wafer pad. The packaging substrate comprises a first surface and a second surface which are opposite, and the first surface is provided with a plurality of golden fingers. The first chip is arranged on the first surface. The second chip is arranged on the side, away from the packaging substrate, of the first chip in a stacked mode. The conductive metal pad or the wafer pad is arranged on the surface, deviating from the packaging substrate, of the second chip. The conductive metal pad or the wafer pad is electrically connected with a chip selection signal of the second chip and is connected with the golden finger through a metal lead. The utility model also provides a semiconductor device comprising the chip packaging module. The pads of the first chip and the second chip are different in arrangement or size, but can be compatibly arranged on the same packaging substrate, so that the development process is shortened, and the development cost is saved.

This invention provides a microelectromechanical device (MEMS) sensor testing device, comprising a testing device body, which includes: a sample placement area for placing N MEMS sensors; a communication switching unit including a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a third output terminal, and a controlled terminal; the first input terminal is electrically connected to the SDI terminal of the MEMS sensor; the second input terminal is electrically connected to the CS terminal of the MEMS sensor; the third input terminal is electrically connected to the SDO terminal of the MEMS sensor; and an SPI interface, whose SCK clock input terminal is electrically connected to the SCK terminal of the MEMS sensor, and whose slave signal input terminal, chip select terminal, and slave signal output terminal are electrically connected to the first output terminal, the second output terminal, and the third output terminal, respectively. Compared with the prior art, this invention can be compatible with testing of SPI three-wire and four-wire communication functions with only a four-wire SPI master control device.

The application relates to the computer technical field and discloses a firmware loading method and device, a computer device and a storage medium, the method is applied to a security monitoring chip, the method comprises the following steps: performing firmware image verification on a plurality of baseboard flash memories of a baseboard management controller through a verification program, and obtaining a verification result of each baseboard flash memory; performing level adjustment on a chip select signal of each baseboard flash memory according to the verification result; receiving a starting signal of the baseboard management controller; determining a target baseboard flash memory for loading firmware from the plurality of baseboard flash memories according to the starting signal; if the verification result of the target baseboard flash memory indicates that the verification is successful, opening a first switch; and if the verification result of the target baseboard flash memory indicates that the verification fails, closing the first switch. The application solves the control conflict problem of the baseboard management controller and the security monitoring chip, and improves the stability of a server.

This invention discloses a DRAM testing method, comprising the following steps: acquiring timing parameters of a DRAM, wherein the DRAM has two RANKs, each RANK having a corresponding chip select pin and a clock enable pin; initializing the DRAM according to the timing parameters; testing the first RANK of the DRAM; after the test is completed, the DRAM controller enters a self-refresh mode; synchronizing the enable clock of the second RANK, activating the initial verification parameters of the second RANK, and switching the chip select clock from the first RANK to the second RANK to test the second RANK; after the second RANK test is completed, the DRAM controller exits the self-refresh mode. According to the DRAM testing method of this invention, switching tests between two RANKs can be performed, and the same address can represent the actual row and column addresses of two parts of the DRAM, thereby achieving a significant increase in the testable DRAM capacity.

The embodiment of the invention provides a method and a device for reducing delay under a command two-phase transmission mechanism. The method comprises the following steps: acquiring a clock signal of a target memory, a chip selection clock signal and delay time corresponding to command operation; in response to the received command signal sent by the target memory, analyzing the command signal according to the clock signal and the chip selection clock signal, and determining a command judgment signal; determining a shift signal according to the clock signal and the chip selection clock signal; determining a delay counting enable signal according to a relationship between the shift signal and a preset shift signal and delay time corresponding to the clock signal and the command operation; a command enable signal is determined according to the delay count enable signal and the command decision signal to perform a command operation at the command address according to the command enable signal. Therefore, the counting start time of the delay clock cycle counting is not influenced by the duration of analyzing the command signal, so that the time for executing the command operation can be accurately determined.

Systems and techniques for detecting connection failures for serially connected worker modules (WMs) are disclosed. A method for detecting connection failures for serially connected WMs includes driving a chip select (CS) signal at a known voltage level to a first IO port of a first WM of a chain of serially connected WMs, propagating the CS signal to a second IO port of the first WM, wherein the second IO port of the first WM is configured to be coupled to a first IO port of a second WM of the chain of serially connected WMs, and determining, based on detecting that a signal at a voltage level different than the known voltage level is present at the first IO port of the second WM, that a connection failure is present between the first WM and the second WM.

This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input / output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command / address decoder. The command / address decoders are configured to receive command and address signals from external contacts of the memory device. The command / address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command / address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command / address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

The present application relates to the field of integrated circuit design, in particular to a device for enabling a parallel bus processor to access CAN bus controller SJA1000 in single step. The device is arranged between the parallel bus processor and SJA1000, and is a bridging circuit for enabling the processor to access SJA1000 in single step; the original timing IO chip select signal of the processor is connected to the ALE pin of SJA1000. The present application further comprises a timing conditioning module, a time-sharing gating module and a driving control module. The present application uses the method of matching timing by hardware, and uses the timing characteristics of the parallel bus processor to enable the parallel bus processor to access SJA1000 in one read-write operation, thus improving the access efficiency of CAN bus.

The present application provides a time-division concurrency method, an apparatus, a computer device, a storage medium, and a computer program product. The method comprises: sending a chip select signal to target slave devices in a single-wire receiving mode, and switching the target slave devices to a bidirectional mode; acquiring target driving rates of the target slave devices; determining an actual distribution rate on the basis of the target driving rates of the target slave devices and the number of the target slave devices; and sequentially sending data frames to corresponding target slave devices on the basis of the actual distribution rate, so as to complete parallel driving of pixel chips corresponding to the target slave devices. In the present application, a master device having an MCU chip select function is used to implement bidirectional communication with slave devices, so as to work in conjunction with the slave devices to complete switching between a single-wire receiving mode configuration function and a bidirectional mode configuration function, thereby implementing concurrent communication of data streams.

Embodiments of the present application provide a base chip, a storage system and a semiconductor structure. The base chip is configured to receive first data and first encoded data and perform first error detection and correction processing in a write phase, the first encoded data is obtained by performing first error correction code encoding processing on the first data, and second error correction code encoding processing is performed on the first data after the first error detection and correction processing. In the write phase, based on a selection signal, the base chip selects to transmit to-be-written data to a storage chip, the to-be-written data is one of initial data or second data, the second data includes second encoded data and the first data after the first error detection and correction processing, and the initial data includes the first data and the first encoded data. In a read phase, based on the selection signal, the base chip selects to transmit the initial data or third data, the third data includes third encoded data and the first data after the second error detection and correction processing. Embodiments of the present application can improve the read-write performance of the storage system.

This invention provides a chip startup method, a chip, an electronic device, and a storage medium. The method includes: after the chip is powered on, acquiring pre-configured startup chip select information; according to the startup chip select information, transferring the startup program of one of at least two external memories to the chip; and executing the transferred startup program to the chip. This invention, by setting startup chip select information and transferring the startup program from the memory to the chip according to the startup chip select information, enables automatic switching startup of the system-level chip upon power-on without adding additional chip pins or requiring dedicated firmware.

Systems, apparatus, articles of manufacture, and methods are disclosed for dynamic chip select modes. An example system includes a memory module including a first rank of dynamic random access devices (DRAMs), a second rank of DRAMs, and a third rank of DRAMs, a first signal line coupled to the memory module, a second signal line coupled to the memory module, and a host memory controller coupled to the first and second signal lines, the host memory controller to generate a multi-bit signal that selects the third rank of DRAM devices, and transmit bits of the multi-bit signal over the second signal line over multiple clock cycles.

A memory module may include a module substrate, a first memory package, a second memory package, and a module controller circuit. The module substrate may include first signal transmission lines and second signal transmission lines. Memory chips of the first memory package may be coupled in common to the first signal transmission lines. Memory chips of the second memory package may be coupled in common to the second signal transmission lines. The module controller circuit may connect a data bus to one of the first signal transmission lines and the second signal transmission lines based on a chip selection signal.

A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

The embodiment of the invention provides a display control chip, a display device, a driving control method of the display device and an electronic device. The display control chip selects a correction mode according to the brightness level of the display equipment, and corrects the received first pixel voltage of any pixel unit to obtain a second pixel voltage; determining a corresponding compensation base value according to the second pixel voltage of the current frame of picture and the second pixel voltage of the previous frame of picture; compensating the first pixel voltage according to the compensation base value to obtain a third pixel voltage; and outputting the third pixel voltage to a corresponding pixel unit to drive the display of the pixel unit.

An apparatus includes one or more controller circuits that are configured to be coupled to a first memory that implements random access and a second memory that implements serial access. A processing unit is configured to generate a map indicating a first set of addresses allocated to the first memory and a second set of addresses allocated to the second memory. The processing unit configures the controller circuit(s) to selectively access either the first memory or the second memory based on the map. In some cases, the first memory is a NOR-based memory, the second memory is a NAND flash memory, and the controller circuit is a serial peripheral interface (SPI) controller circuit. Selectively accessing the first memory or the second memory can include asserting a signal on a first or second chip select pin.

This disclosure provides a semiconductor memory device and a memory system. The semiconductor memory device includes: a chip module comprising multiple memory chips connected to adjacent memory chips via connectors; each memory chip includes an electrical connection portion; the connector includes a first conductive structure electrically connected to the electrical connection portions of adjacent memory chips; and a control unit connected to each memory chip and configured to control the opening or closing of the signal transmission channels of each memory chip in response to a chip selection signal. The memory capacity can be expanded via the connector connection, which is simple and easy to implement. The control unit can control the opening or closing of the signal transmission channels of each memory chip according to the received chip selection signal. Thus, the expansion function of the semiconductor memory device can be conveniently opened or closed according to actual needs, and the number of available memory chips can be adjusted, thereby flexibly controlling the memory capacity and better balancing memory capacity and power consumption.

This application relates to a storage device, a method, apparatus, and device for capacity detection and control of the storage device. The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end is connected to the back-end, and the back-end is connected to the first type of flash memory via a chip select signal. During power-up of the storage device, the back-end scans the chip select signal using first-type firmware to determine the target chip select signal connected to the first type of flash memory, obtains the capacity parameters of the first type of flash memory, and determines the capacity of the storage device based on the capacity parameters and the target chip select signal. After the back-end determines the capacity of the storage device, the front-end reissues second-type firmware to the back-end. The back-end uses the second-type firmware to input and output data according to the capacity of the storage device. This application solves the memory usage problem caused by adding capacity detection functionality in conventional technologies.

This application discloses a data processing system, method, and apparatus based on a storage device. The method includes: acquiring a data processing request; acquiring a preset enable relationship table, which includes enable relationships between chip select signal processing units; determining a first chip select signal logic unit corresponding to the target data, and determining a second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit based on the enable relationships; performing an enable operation on the second chip select signal logic unit, and performing a target processing operation on the target data in the first chip select signal logic unit. This application, by utilizing the enable relationships in the preset enable relationship list to determine the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit corresponding to the target data, and then performing an enable operation on the second chip select signal logic unit before performing data processing operations, meets the high transmission rate requirements during data processing and improves the read / write performance of the storage device.