Digital in-memory computing array device

A computing array and digital technology, which is applied in the field of digital memory computing array devices, can solve problems such as temperature and noise, and the influence of analog domain calculations

Active Publication Date: 2021-06-25
中科南京智能技术研究院
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  • Abstract
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Problems solved by technology

Analog domain calculations are susceptible to envi

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  • Digital in-memory computing array device
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Embodiment Construction

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0022] The object of the present invention is to provide a computing array device in a digital memory, which realizes multiplying and accumulating with a digital method, and improves the computing precision.

[0023] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[00...

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Abstract

The invention relates to a digital in-memory computing array device, which comprises 256 row * 64 column in-memory computing modules, each in-memory computing module comprises a bit cell, a tube T7, a tube 8 and an XNOR gate, and the tube T7 and the tube 8 form a transmission gate; the weight storage point Q of the bit cell is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the first input end of the XNOR gate, the second input end of the XNOR gate is connected with an input signal, the output of the XNOR gate serves as the output of the bit cell, the grid electrode of the tube T7 is connected with a control signal RE, and the grid electrode of the tube T8 is connected with a control signal REN; an input signal input by each bit unit and the weight storage point Q are subjected to XNOR operation through an XNOR gate; and a column of bit cells is calculated each time, and thus accumulating 1bit outputs of 256 bit cells and then outputting a 9bit multiply-accumulate result. According to the invention, the calculation precision is improved.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a digital in-memory computing array device. Background technique [0002] Deep convolutional neural networks (DCNNs) continue to demonstrate improvements in inference accuracy, and deep learning is moving to edge computing. This development has spurred work on low-resource machine learning algorithms and hardware to accelerate them. The most common operation in DCNNs is multiply and accumulate (MAC), which controls power and latency. MAC operations have high regularity and parallelism, so they are very suitable for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of conventional digital accelerators. Therefore, computing in memory (CIM) is becoming more and more attractive for DCNN acceleration. [0003] The current storage and calculation arrays are basically based on the calculation method in the analog domain. Th...

Claims

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Application Information

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IPC IPC(8): G11C11/419G11C7/10G11C7/12G11C8/08G11C8/10G06F7/498G06F7/575
CPCG06F7/4983G06F7/575G11C7/1096G11C7/12G11C8/08G11C8/10G11C11/419
Inventor 乔树山黄茂森尚德龙周玉梅
Owner 中科南京智能技术研究院
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